W40S11-02
Signaling from System Core Logic
Start Condition
Slave Address
(First Byte)
SDATA
MSB
1
1
0
1
0
0
1
LSB
0
MSB
Stop C
Command Code
(Second Byte)
LSB
Byte Count
(Third Byte)
MSB
MSB
Last Data Byte
(Last Byte)
LS
SCLOCK
1
2
3
4
5
6
7
8
A
1
2
3
4
5
6
7
8
A
1
2
3
4
1
2
3
4
5
6
7
8
SDATA
Signaling by Clock Device
Acknowledgment Bit
from Clock Device
Figure 2. Serial Data Bus Write Sequence
SDATA
t
SPF
t
LOW
SCLOCK
t
STHD
t
R
t
HIGH
t
F
t
DSU
t
DHD
t
SP
t
SPSU
t
STHD
t
SPSU
Figure 3. Serial Data Bus Timing Diagram
Absolute Maximum Ratings
Stresses greater than those listed in this table may cause
permanent damage to the device. These represent a stress
rating only. Operation of the device at these or any other condi-
Parameter
V
DD
, V
IN
T
STG
T
A
T
B
Description
Voltage on any pin with respect to GND
Storage Temperature
Operating Temperature
Ambient Temperature under Bias
tions above those specified in the operating sections of this
specification is not implied. Maximum conditions for extended
periods may affect reliability.
Rating
–0.5 to +7.0
–65 to +150
0 to +70
–55 to +125
Unit
V
°C
°C
°C
Rev 1.0, Dec. 01, 2006
Page 6 of 9
SPECTRALINEAR [ SPECTRALINEAR INC ]
