M50FLW080A, M50FLW080B
When the Program Suspend Status bit is ‘0’, the
Program/Erase Controller is active, or has com-
pleted its operation. When the bit is ‘1’, a Program/
Erase Suspend command has been issued and
the memory is waiting for a Program/Erase Re-
sume command.
When a Program/Erase Resume command is is-
sued, the Program Suspend Status bit returns to
‘0’.
Block/Sector Protection Status (Bit SR1). The
Block/Sector Protection Status bit can be used to
identify if the Program or Erase operation has tried
to modify the contents of a protected block or sec-
tor. When the Block/Sector Protection Status bit is
reset to ‘0’, no Program or Erase operations have
been attempted on protected blocks or sectors
since the last Clear Status Register command or
hardware reset. When the Block/Sector Protection
Status bit is ‘1’, a Program or Erase operation has
been attempted on a protected block or sector.
Once it is set to ‘1’, the Block/Sector Protection
Status bit can only be reset to ‘0’ by a Clear Status
Register command or by a hardware reset. If it is
set to ‘1’, it should be reset before a new Program
or Erase command is issued, otherwise the new
command will appear to have failed, too.
Using the A/A Mux Interface, the Block/Sector Pro-
tection Status bit is always ‘0’.
Reserved (Bit SR0). Bit 0 of the Status Register
is reserved. Its value should be masked.
Table 14. Status Register Bits
Operation
SR7
‘0’
SR6
SR5
‘0’
SR4
‘0’
SR3
‘0’
SR2
‘0’
SR1
‘0’
(1)
Program active
X
(1)
Program suspended
‘1
‘0’
‘0’
‘0’
‘1’
‘0’
X
(1)
Program completed successfully
‘1’
‘0’
‘0’
‘0’
‘0’
‘0’
X
(1)
Program failure due to V Error
‘1’
‘0’
‘1’
‘1’
‘0’
‘0’
PP
X
Program failure due to Block/Sector Protection
(FWH/LPC Interface only)
(1)
‘1’
‘0’
‘1’
‘0’
‘0’
‘1’
X
(1)
Program failure due to cell failure
Erase active
‘1’
‘0’
‘1’
‘1’
‘1’
‘0’
‘0’
‘0’
‘0’
‘1’
‘1’
‘0’
‘0’
‘0’
‘0’
‘0’
‘0’
‘0’
‘0’
‘1’
‘0’
‘0’
‘0’
‘0’
‘0’
‘0’
‘0’
‘0’
‘0’
‘0’
X
‘0’
‘1’
‘0’
‘0’
Erase suspended
Erase completed successfully
Erase failure due to V Error
PP
Erase failure due to Block/Sector Protection
(FWH/LPC Interface only)
‘1’
‘1’
‘0’
‘0’
‘1’
‘1’
‘0’
‘0’
‘0’
‘0’
‘0’
‘0’
‘1’
‘0’
Erase failure due to failed cell(s) in block or sector
Note: 1. For Program operations during Erase Suspend, the SR6 bit is ‘1’, otherwise the SR6 bit is ‘0’.
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STMICROELECTRONICS [ ST ]
