M95040, M95020, M95010
SUMMARY DESCRIPTION
The M95040 is a 4 Kbit (512 x 8) electrically eras-
able programmable memory (EEPROM), access-
ed by a high speed SPI-compatible bus. The other
members of the family (M95020 and M95010) are
identical, though proportionally smaller (2 and 1
Kbit, respectively).
Each device is accessed by a simple serial inter-
face that is SPI-compatible. The bus signals are C,
D and Q, as shown in
and
The device is selected when Chip Select (S) is tak-
en Low. Communications with the device can be
interrupted using Hold (HOLD). WRITE instruc-
tions are disabled by Write Protect (W).
Figure 2. Logic Diagram
Note: See
section for package dimen-
sions, and how to identify pin-1.
Figure 3. DIP, SO and TSSOP Connections
M95xxx
S
Q
W
VSS
1
2
3
4
8
7
6
5
AI01790D
VCC
HOLD
C
D
VCC
Table 2. Signal Names
C
Serial Clock
Serial Data Input
Serial Data Output
Chip Select
Write Protect
Hold
Supply Voltage
Ground
D
C
S
W
HOLD
M95xxx
Q
D
Q
S
W
HOLD
V
CC
VSS
AI01789C
V
SS
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