VIPER27
Operation descriptions
When the feedback pin voltage reaches the threshold VFBlin an internal current generator
starts to charge the feedback capacitor (CFB) and when the feedback voltage reaches the
VFBolp threshold, the converter is turned off and the start up phase is activated with reduced
value of IDDch to 0.6 mA, see Table 7 on page 6.
During the first start up phase of the converter, after the soft-start up time, tSS, the output
voltage could force the feedback pin voltage to rise up to the VFBolp threshold that switches
off the converter itself.
To avoid this event, the appropriate feedback network has to be selected according to the
output load. More the network feedback fixes the compensation loop stability. The Figure 28
on page 22 and Figure 29 show the two different feedback networks.
The time from the over load detection (VFB = VFBlin) to the device shutdown
(VFB = VFBolp) can be set by CFB value (see Figure 28 on page 22 and Figure 29), using the
formula:
Equation 5
V
FBolp – VFBlin
---------------------------------------
×
TOLP – delay = CFB
3μA
In the Figure 28, the capacitor connected to FB pin (CFB) is part of the compensation circuit
as well as it needs to activate the over load protection (see equation 5).
After the start up time, tSS, during which the feedback voltage is fixed at VFBlin, the output
capacitor could not be at its nominal value and the controller interprets this situation as an
over load condition. In this case, the OLP delay helps to avoid an incorrect device shut down
during the start up phase.
Owing to the above considerations, the OLP delay time must be long enough to by-pass the
initial output voltage transient and check the over load condition only when the output
voltage is in steady state. The output transient time depends from the value of the output
capacitor and from the load.
When the value of the CFB capacitor calculated for the loop stability is too low and cannot
ensure enough OLP delay, an alternative compensation network can be used and it is
showed in Figure 29 on page 22.
Using this alternative compensation network, two poles (fPFB, fPFB1) and one zero (fZFB) are
introduced by the capacitors CFB and CFB1 and the resistor RFB1
.
The capacitor CFB introduces a pole (fPFB) at higher frequency than fZB and fPFB1. This pole
is usually used to compensate the high frequency zero due to the ESR (equivalent series
resistor) of the output capacitance of the fly-back converter.
The mathematical expressions of these poles and zero frequency, considering the scheme
in Figure 29 are reported by the equations below:
Equation 6
1
fZFB
=
2⋅ π⋅CFB1 ⋅RFB1
Doc ID 15133 Rev 5
21/31
STMICROELECTRONICS [ ST ]
