Operation descriptions
Equation 7
VIPER27
RFB(DYN) + RFB1
fPFB
=
2 ⋅ π ⋅ CFB
⋅
(
RFB(DYN) ⋅RFB1
)
)
Equation 8
1
fPFB1
=
2⋅ π⋅CFB1
⋅
(
RFB1 +RFB(DYN)
The RFB(DYN) is the dynamic resistance seen by the FB pin.
The CFB1 capacitor fixes the OLP delay and usually CFB1 results much higher than CFB
.
The Equation 5 can be still used to calculate the OLP delay time but CFB1 has to be
considered instead of CFB. Using the alternative compensation network, the designer can
satisfy, in all case, the loop stability and the enough OLP delay time alike.
Figure 28. FB pin configuration
From sense FET
PWM
To PWM Logic
+
PWM
CONTROL
-
Cfb
BURST
BURST-MODE
LOGIC
BURST-MODE
REFERENCES
OLP comparator
+
To disable logic
-
4.8V
Figure 29. FB pin configuration
From sense FET
PWM
+
To PWM Logic
PWM
CONTROL
-
Rfb1
Cfb
BURST
BURST-MODE
LOGIC
Cfb1
BURST-MODE
REFERENCES
OLP comparator
To disable logic
+
-
4.8V
22/31
Doc ID 15133 Rev 5
STMICROELECTRONICS [ ST ]
