VN750-E / VN750S-E / VN750PT-E / VN750B5-E
Figure 5.
OPEN LOAD STATUS TIMING (with external pull-up)
OVERTEMP STATUS TIMING
T > T
I
< I
OUT OL
V
OUT
> V
OL
j
jsh
V
IN
V
IN
V
STAT
V
STAT
t
t
t
DOL(off)
t
DOL(on)
SDL
SDL
Table 12. Truth Table
CONDITIONS
INPUT
OUTPUT
STATUS
L
H
L
H
H
H
Normal Operation
Current Limitation
L
H
H
L
X
X
H
) H
) L
(T < T
(T > T
j
j
TSD
TSD
L
H
L
L
H
L
Overtemperature
Undervoltage
Overvoltage
L
H
L
L
X
X
L
H
L
L
H
H
L
H
H
H
L
H
Output Voltage > V
OL
L
H
L
H
H
L
Output Current < I
OL
Figure 6. Switching time Waveforms
VOUTn
90%
80%
dVOUT/dt(off)
dVOUT/dt(on)
10%
t
VINn
td(on)
td(off)
t
6/31
STMICROELECTRONICS [ ST ]
