TSL2571
LIGHT-TO-DIGITAL CONVERTER
TAOS117A − FEBRUARY 2011
Wait Characteristics, V
DD
= 3 V, T
A
= 255C, WEN = 1 (unless otherwise noted)
PARAMETER
Wait step size
Wait number of integration steps
TEST CONDITIONS
WTIME = 0xFF
CHANNEL
MIN
2.58
1
TYP
2.72
MAX
2.9
256
UNIT
ms
steps
AC Electrical Characteristics, V
DD
= 3 V, T
A
= 255C (unless otherwise noted)
PARAMETER
†
f
(SCL)
t
(BUF)
t
(HDSTA)
t
(SUSTA)
t
(SUSTO)
t
(HDDAT)
t
(SUDAT)
t
(LOW)
t
(HIGH)
t
F
t
R
C
i
†
TEST CONDITIONS
MIN
0
1.3
0.6
0.6
0.6
0
100
1.3
0.6
TYP
MAX
400
UNIT
kHz
μs
μs
μs
μs
μs
ns
μs
μs
Clock frequency (I
2
C only)
Bus free time between start and stop condition
Hold time after (repeated) start condition. After
this period, the first clock is generated.
Repeated start condition setup time
Stop condition setup time
Data hold time
Data setup time
SCL clock low period
SCL clock high period
Clock/data fall time
Clock/data rise time
Input pin capacitance
300
300
10
ns
ns
pF
Specified by design and characterization; not production tested.
PARAMETER MEASUREMENT INFORMATION
t
(LOW)
t
(R)
t
(F)
SCL
V
IH
V
IL
t
(HDSTA)
t
(BUF)
t
(HDDAT)
V
IH
V
IL
t
(HIGH)
t
(SUSTA)
t
(SUDAT)
t
(SUSTO)
SDA
P
Stop
Condition
S
Start
Condition
Start
S
Stop
t
(LOWSEXT)
SCL
ACK
SCL
ACK
t
(LOWMEXT)
t
(LOWMEXT)
t
(LOWMEXT)
P
SCL
SDA
Figure 1. Timing Diagrams
The
LUMENOLOGY
r
Company
Copyright
E
2011, TAOS Inc.
r
r
www.taosinc.com
5
TAOS [ TEXAS ADVANCED OPTOELECTRONIC SOLUTIONS ]
