L67132/L67142
AC Parameters
L67132–45
L67142–45
L67132–55
L67142–55
L67132–70
L67142–70
SYMBOL
PARAMETER
UNIT
MIN.
MAX.
MIN.
MAX.
MIN.
MAX.
BUSY TIMING (For L 67132 only)
t
t
BUSY Access time to address
BUSY Disable time to address
BUSY Access time to Chip Select
BUSY Disable time to Chip Select
Write Pulse to data delay (40)
Write data valid to read data delay (40)
Arbitration priority set–up time (41)
BUSY disable to valid data
–
35
–
45
–
50
ns
ns
ns
ns
ns
ns
ns
ns
BAA
BDA
–
–
–
–
–
5
–
35
30
–
–
–
–
–
5
–
40
35
–
–
–
–
–
5
–
40
50
t
BAC
BDC
t
25
30
40
t
70
80
90
WDD
t
45
55
70
DDD
t
–
–
–
APS
t
Note 42
Note 42
Note 42
BDD
BUSY TIMING (For L 67142 only)
t
Write to BUSY input (43)
0
20
–
–
–
0
30
–
–
–
0
30
–
–
–
ns
ns
ns
ns
WB
WH
t
Write hold after BUSY (44)
Write pulse to data delay (45)
Write data valid to read data delay (45)
t
70
45
80
55
90
70
WDD
t
–
–
–
DDD
Notes : 40. Port-to-port delay through RAM cells from writing port to reading port, refer to “Timing Waveform of Read with
BUSY (For L67132 only)”.
41. To ensure that the earlier of the two ports wins.
42.
t
is a calculated parameter and is the greater of 0, t
– t (actual) or t
WP
– t
DW
(actual).
BDD
WDD
DDD
43. To ensure that the write cycle is inhibited during contention.
44. To ensure that a write cycle is completed after contention.
45. Port-to-port delay through RAM cells from writing port to reading port, refer to “Timing Waveforms of Read
with Port to port delay (For L67142 only)”.
10
MATRA MHS
Rev. D (19 Fev. 97)
TEMIC [ TEMIC SEMICONDUCTORS ]
