MATRA MHS
L 67205
8K
×
9 / 3.3 Volts CMOS Parallel FIFO
Introduction
The L67205 implements a first-in first-out algorithm,
featuring asynchronous read/write operations. The FULL
and EMPTY flags prevent data overflow and underflow.
The Expansion logic allows unlimited expansion in word
size and depth with no timing penalties. Twin address
pointers automatically generate internal read and write
addresses, and no external address information are
required for the MHS FIFOs. Address pointers are
automatically incremented with the write pin and read
pin. The 9 bits wide data are used in data communications
applications where a parity bit for error checking is
necessary. The Retransmit pin reset the Read pointer to
zero without affecting the write pointer. This is very
useful for retransmitting data when an error is detected in
the system.
Using an array of eigh transistors (8 T) memory cell and
fabricated with the state of the art 1.0
µm
lithography
named SCMOS, the L 67205 combine an extremely low
standby supply current (typ = 1.0
µA)
with a fast access
time at 55 ns over the full temperature range. All versions
offer battery backup data retention capability with a
typical power consumption at less than 5
µW.
For military/space applications that demand superior
levels of performance and reliability the L 67205 is
processed according to the methods of the latest revision
of the MIL STD 883 (class B or S) and/or ESA SCC 9000.
Features
D
D
D
D
First-in first-out dual port memory
Single supply 3.3
±
0.3 volts
8192
×
9 organisation
Fast access time
55, 60, 65 ns, commercial, industrial military
and automotive
D
Wide temperature range :
– 55
°C
to + 125
°C
D
67205L low power
67205V very low power
D
D
D
D
D
D
D
Fully expandable by word width or depth
Asynchronous read/write operations
Empty, full and half flags in single device mode
Retransmit capability
Bi-directional applications
Battery back-up operation 2 V data retention
High performance SCMOS technology
Rev. C (10/11/94)
1
TEMIC [ TEMIC SEMICONDUCTORS ]
