MATRA MHS
Pin Names
NAMES
I0–8
Q0–8
W
R
RS
EF
Inputs
Outputs
Write Enable
Read Enable
Reset
Empty Flag
L 67205
DESCRIPTION
NAMES
FF
XO/HF
XI
FL/RT
VCC
GND
DESCRIPTION
Full Flag
Expansion Out/Half-Full Flag
Expansion IN
First Load/Retransmit
Power Supply
Ground
Signal Description
Data In (I
0
- I
8
)
Data inputs for 9 - bit data
pointers to the first location. A reset is required after
power-up before a write operation can be enabled. Both
the Read Enable (R) and Write Enable (W) inputs must be
in the high state during the period shown in figure 1 (i.e.
t
RSS
before the rising edge of RS) and should not change
until t
RSR
after the rising edge of RS. The Half-Full flag
(HF will be reset to high after Reset (RS).
Reset (RS)
Reset occurs whenever the Reset (RS) input is taken to a
low state. Reset returns both internal read and write
Figure 1. Reset.
Notes :
1. EF, FF and HF may change status during Reset, but flags will be valid at t
RSC
.
2. W and R = VIH around the rising edge of RS.
Write Enable (W)
A write cycle is initiated on the falling edge of this input
if the Full Flag (FF) is not set. Data set-up and hold times
must be maintained in the rise time of the leading edge of
the Write Enable (W). Data is stored sequentially in the
Ram array, regardless of any current read operation.
Once half of the memory is filled, and during the falling
edge of the next write operation, the Half-Full Flag (HF)
will be set to low and remain in this state until the
difference between the write and read pointers is less than
or equal to half of the total available memory in the
device. The Half-Full Flag (HF) is then reset by the rising
edge of the read operation.
To prevent data overflow, the Full Flag (FF) will go low,
inhibiting further write operations. On completion of a
valid read operation, the Full Flag (FF) will go high after
TRFF, allowing a valid write to begin. When the FIFO
Rev. C (10/11/94)
3
TEMIC [ TEMIC SEMICONDUCTORS ]
