POWER DISSIPATION
The architecture of the converter, the semiconductor fabrica-
tion process, and a careful design allow the ADS8324 to
convert at up to a 50kHz rate while requiring very little
power. Still, for the absolute lowest power dissipation, there
are several things to keep in mind.
The power dissipation of the ADS8324 scales directly with
the conversion rate. Therefore, the first step to achieving the
lowest power dissipation is to find the lowest conversion rate
that will satisfy the requirements of the system.
In addition, the ADS8324 is in power-down mode under two
conditions: when the conversion is complete and whenever
CS is HIGH (see Figure 5). Ideally, each conversion should
occur as quickly as possible, preferably at a 1.2MHz clock
rate. This way, the converter spends the longest possible
time in the power-down mode. This is very important as the
converter not only uses power on each DCLOCK transition
(as is typical for digital CMOS components) but also uses
some current for the analog circuitry, such as the compara-
tor. The analog section dissipates power continuously, until
the power-down mode is entered.
0.9V
3kΩ
D
OUT
30pF
C
LOAD
Test Point
D
OUT
t
r
t
f
V
OH
V
OL
Voltage Waveforms for D
OUT
Rise and Fall Times, t
r
, t
f
Load Circuit for t
dDO
, t
r
, and t
f
Test Point
DCLOCK
V
IL
t
dDO
D
OUT
t
hDO
Voltage Waveforms for D
OUT
Delay Times, t
dDO
V
OH
V
OL
D
OUT
3kΩ
30pF
C
LOAD
Load Circuit for t
dis
and t
en
V
CC
t
dis
Waveform 2, t
en
t
dis
Waveform 1
CS/SHDN
V
IH
CS/SHDN
DCLOCK
5
6
D
OUT
Waveform 1
(1)
t
dis
D
OUT
Waveform 2
(2)
Voltage Waveforms for t
dis
90%
10%
D
OUT
t
en
Voltage Waveforms for t
en
V
OL
B11
NOTES: (1) Waveform 1 is for an output with internal conditions such that the output
is HIGH unless disabled by the output control. (2) Waveform 2 is for an output with
internal conditions such that the output is LOW unless disabled by the output control.
FIGURE 6. Timing Diagrams and Test Circuits for the Parameters in Table I.
10
ADS8324
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