DIGITAL INTERFACE
SIGNAL LEVELS
The CMOS digital output (D
OUT
) will swing from 0V to
V
CC
. If V
CC
is 3V, and this output is connected to a 5V
CMOS logic input, then that IC may require more supply
current than normal and may have a slightly longer propaga-
tion delay.
SERIAL INTERFACE
The ADS8324 communicates with microprocessors and
other digital systems via a synchronous 3-wire serial inter-
face, as shown in Figure 5 and Table I. The DCLOCK signal
synchronizes the data transfer with each bit being transmit-
ted on the falling edge of DCLOCK. Most receiving systems
will capture the bitstream on the rising edge of DCLOCK.
However, if the minimum hold time for D
OUT
is acceptable,
the system can use the falling edge of DCLOCK to
capture each bit.
A falling CS signal initiates the conversion and data transfer.
The first 4.5 to 5.0 clock periods of the conversion cycle are
used to sample the input signal. After the fifth falling
DCLOCK edge, D
OUT
is enabled and will output a LOW
value for one clock period. For the next 16 DCLOCK
periods, D
OUT
will output the conversion result, most sig-
nificant bit first followed by two zeros on clock cycles 15
and 16. After the two zero “dummy bits” have been output,
subsequent clocks will repeat the output data but in a least
significant bit first format starting with a zero.
CS must be taken HIGH following a conversion in order to
place DOUT in tri-state. Subsequent clocks will have no
effect on the converter. A new conversion is initiated only
when CS has been taken HIGH and returned LOW.
SYMBOL
t
SMPL
t
CONV
t
CYC
t
CSD
t
SUCS
t
hDO
t
dDO
t
dis
t
en
t
f
t
r
DESCRIPTION
Analog Input Sample Time
Conversion Time
Throughput Rate
CS Falling to
DCLOCK LOW
CS Falling to
DCLOCK Rising
DCLOCK Falling to
Current D
OUT
Not Valid
DCLOCK Falling to Next
D
OUT
Valid
CS Rising to D
OUT
Tri-State
DCLOCK Falling to D
OUT
Enabled
D
OUT
Fall Time
D
OUT
Rise Time
MIN
4.5
TYP
MAX
5.0
UNITS
Clk Cycles
Clk Cycles
16
50
0
kHz
ns
50
ns
5
20
100
50
100
50
75
250
100
200
150
200
ns
ns
ns
ns
ns
ns
TABLE I. Timing Specifications (V
CC
= 1.8V) –40°C to
+85°C.
See Figure 6 for test conditions.
DATA FORMAT
The output data from the ADS8324 is in Binary Two’s
Complement format, as shown in Table II. This table repre-
sents the ideal output code for the given input voltage and
does not include the effects of offset, gain error, or noise.
DESCRIPTION
Full-Scale Range
Least Significant
Bit (LSB)
+Full Scale
Midscale
Midscale – 1LSB
–Full Scale
ANALOG VALUE
2 • V
REF
2 • V
REF
/16384
BINARY CODE
+V
REF
– 1 LSB
0V
0V – 1 LSB
–V
REF
0111 1111 1111 1100
0000 0000 0000 0000
1111 1111 1111 1100
1000 0000 0000 0000
HEX CODE
7FFC
0000
FFFC
8000
DIGITAL OUTPUT
BINARY TWO’S COMPLEMENT
TABLE II. Ideal Input Voltages and Output Codes.
Complete Cycle
CS/SHDN
t
SUCS
Sample
DCLOCK
t
CSD
D
OUT
Hi-Z
0
t
SMPL
B13 B12 B11 B10 B9
(MSB)
B8
B7
B6
B5
B4
B3 B2 B1
B0 0
(LSB)
0
Use positive clock edge for data transfer
Hi-Z
Conversion
Power Down
t
CONV
NOTE: Minimum 22 clock cycles required for 14-bit conversion. Shown are 24 clock cycles.
If CS remains LOW at the end of conversion, a new datastream with LSB-first is shifted out again.
FIGURE 5. ADS8324 Basic Timing Diagrams.
ADS8324
SBAS172A
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