bq2201
As the supply continues to fall past V
PFD
, an internal
switching device forces V
OUT
to one of the two external
backup energy sources. CE
CON
is held high by the V
OUT
energy source.
During power-up, V
OUT
is switched back to the V
CC
sup-
ply as V
CC
rises above the backup cell input voltage
sourcing V
OUT
. The CE
CON
output is held inactive for
time t
CER
(120 ms maximum) after the supply has
reached V
PFD
, independent of the CE input, to allow for
processor stabilization.
During power-valid operation, the CE input is fed
through to the CE
CON
output with a propagation delay
of less than 10ns. Nonvolatility is achieved by hardware
hookup, as shown in Figure 1.
A valid isolation signal requires CE low as V
CC
crosses
both V
PFD
and V
SO
during a power-down. See Figure 2.
Between these two points in time, CE must be brought
to the point of (0.48 to 0.52)*V
CC
and held for at least
700ns. The isolation signal is invalid if CE exceeds
0.54*V
CC
at any point between V
CC
crossing V
PFD
and
V
SO
.
The appropriate battery is connected to V
OUT
and CE
CON
immediately on subsequent application and removal of V
CC
.
Energy Cell Inputs—BC1, BC2
Two primary backup energy source inputs are provided
on the bq2201. The BC
1
and BC
2
inputs accept a 3V pri-
mary battery, typically some type of lithium chemistry.
If no primary cell is to be used on either BC
1
or BC
2
, the
unused input should be tied to V
SS
.
If both inputs are used, during power failure the V
OUT
output is fed only by BC
1
as long as it is greater than
2.5V. If the voltage at BC
1
falls below 2.5V, an internal
isolation switch automatically switches V
OUT
from BC
1
to BC
2
.
To prevent battery drain when there is no valid data to
retain, V
OUT
and CE
CON
are internally isolated from
BC
1
and BC
2
by either of the following:
s
s
VPFD
VCC
VSO
CE
700ns
0.5 VCC
TD220101.eps
Initial connection of a battery to BC
1
or BC
2
, or
Presentation of an isolation signal on CE.
Figure 2. Battery Isolation Signal
5V
VCC
From Address Decoder
CE
bq2201
BC1
THS
3V
Primary
Cell
VSS
BC2
3V
Primary
Cell
CECON
CE
CMOS
SRAM
VOUT
VCC
FG220101.eps
Figure 1. Hardware Hookup (5% Supply Operation)
Oct. 1998 D
2
TI [ TEXAS INSTRUMENTS ]
