SLWS208 – JANUARY 2008
www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
AVAILABLE OPTIONS
T
A
(1)
PACKAGED DEVICE
(1)
352-ball S-PBGA package, 27 mm
×
27 mm
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
Web site at
GC5322 FUNCTIONAL BLOCK DIAGRAM
RESETB SYNC SYNC INT
UPDATA UPADDR
OEB RDB WRB CEB
OUT
3
16
10
TCK
TRSTB
TDI
TMS
TDO
4
GC5322
IPDL
Detect
Gain
BBin
16
BBFR
MFIO[19:18]
2
(Optional;
additional
2 LSBs)
Pilot
Insertion
AntCal
Insertion
Power
Meter
Medium NarrowBand DUC
Band NarrowBand DUC
Wide DUC NarrowBand DUC
Band
DUC Medium NarrowBand DUC
Band NarrowBand DUC
DUC NarrowBand DUC
+
Medium NarrowBand DUC
Band NarrowBand DUC
Wide DUC NarrowBand DUC
Band
DUC Medium NarrowBand DUC
Band NarrowBand DUC
DUC NarrowBand DUC
CFR
MPU Interface
JTAG
ADVANCE INFORMATION
Fractional
Farrow
Resampler
Circular
Limiter
BB
PLL
DPD
PLL
BBCLK
DPDCLK
(LVDS)
FB
(LVDS)
18 Pairs
ADC
Interface
Real to Complex
(or Bypass)
Feedback
Equalizer
Feedback NL
Correction
SYNCD
TX
(LVDS)
19 Pairs
DAC
Interface
Bulk Interpolation
+ Mixer
Transmit
Equalizer
(LVDS)
DPD
Capture Buffers
DUCs in
1-Chn Mode
DUCs in
2-Chn Mode
DUCs in
6-Chn Mode
BB Clock Domain
DPD Clock Domain
B0279-01
2
Product Folder Link(s):
Copyright © 2008, Texas Instruments Incorporated
TI [ TEXAS INSTRUMENTS ]
