SLWS208 – JANUARY 2008
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Users can specify the filter characteristics of the DUC programmable finite impulse response (PFIR),
compensating finite impulse response (CFIR), and cascade integrator comb (CIC) filters. Users can also specify
the center frequencies of each carrier with a resolution of 0.25
µHz.
Additional controls available in the DUCs
include bulk and fractional time delay adjustments, phase adjustments, and equalization. The maximum DUC
output bandwidth is 40 MHz. The maximum DUC complex output sampling rate is 70 MSPS.
Crest Factor Reduction (CFR)
The GC5322 CFR block selectively reduces the peak-to-average ratio (PAR) of wideband digital signals provided
in quadrature (I and Q) format, such as those used in third-generation (3G) code division multiple access
(CDMA) wireless applications. The CFR block can reduce the PAR of W-CDMA Test Model 1 and Test Model 3
signals down to 6.5 dB output PAR while still meeting all 3GPP requirements for ACLR, composite EVM, and
peak code domain error (PCDE). The CFR block accepts input sampling rates up to 70 MSPS complex either
from the DUC block or directly from the input interface.
Fractional Farrow Resampler (FR)
The CFR block output signal bandwidth is up to 40 MHz wide, sampled at up to 70 MSPS. However; the DPD
block provides PA compensation over an expansion bandwidth of up to 140 MHz, using a complex sampling rate
of up to 140 MSPS. To provide the requisite sampling rate of up to 140 MSPS at the input to DPD, the output of
the CFR block must be resampled. The GC5322 performs this (nominally 2×) upsampling function using a
Farrow filter resampler. The user-programmable Farrow resampler supports upsampling rates from 1× to 64×,
with 16-bit precision on the interpolation ratio. It marks the transition of the input clock domain (driven by the
input interface clock) to the transmit domain (driven by the DAC sampling clock).
ADVANCE INFORMATION
Digital Predistortion (DPD)
The DPD block provides predistortion for up to Nth-order nonlinearities, and can correct multiple orders and
lengths of PA memory effects. The predistortion correction terms are computed by an external processor (for
example, TI TMS320C6727 DSP) based on PA feedback data captured in the GC5322. The external processor
reads the captured data buffers from the GC5322 and writes back the newly computed DPD correction terms on
a continuous basis. TI provides a base delivery of 'C6727 software to GC5322 customers that achieves a typical
ACLR improvement of 20 dB to 30 dB or more when compared to a PA without DPD. The standard EMIF bus
allows the user to provide an alternate DPD adaptation algorithm and DSP embodiment, if desired.
Bulk Upconverter (BUC)
The bulk upconverter block can interpolate the DPD block output by 1.5×, 2×, 3×, or 6×. The complex-to-real
converter block optionally modifies the DPD complex output stream into a real output stream. The bulk
upconverter has flexible mixing options between its various interpolation stages. When used in combination, the
bulk upconverter and the complex-to-real functions allow the GC5322 to output a 16-bit real signal at up to 840
MSPS, or a complex signal at up to 420 MSPS. Next-generation data converters can accept sampling rates as
high as 1 GSPS and sample widths of 16 bits. In a typical application, the bulk upconverter outputs a
737.28-MSPS real sampling rate (16 bits/sample) directly to the DAC on a modified center frequency of 184.32
MHz (1/4 of the 737.28-MSPS sampling rate). The bulk upconverter has multiple high-speed, low-voltage,
single-ended/differential output interfaces to existing and future TI DACs.
Feedback Path (FB)
The feedback block accepts an external A/D converter input that represents the PA output signal. This feedback
signal is processed by a feedback path that adjusts for gain, frequency, and phase anomalies in the RF-to-IF
downconversion chain. The feedback path includes an 8-tap complex receive equalizer and lookup tables that
can compensate for the nonlinearities in the RF-to-IF part of the feedback chain. The block also includes a
real-to-complex conversion to facilitate signal processing. The GC5322 connects directly to the ADS5444,
ADS5545, ADS5546, and ADS5517 among others, without requiring external components. The GC5322
simplifies timing by providing a FIFO for each ADC port, sampling the input data using the ADC data-ready
signal.
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