MSP430F663x
SLAS566C – JUNE 2010 – REVISED AUGUST 2012
Table 3. Terminal Functions (continued)
TERMINAL
NAME
NO.
PZ
16
ZQW
H1
I/O
General-purpose digital I/O
Conversion clock output ADC (not available on F6632, F6631, F6630 devices)
DMA external trigger input
P2.0/P2MAP0
17
G4
I/O
General-purpose digital I/O with port interrupt and mappable secondary function
Default mapping: USCI_B0 SPI slave transmit enable; USCI_A0 clock input/output
General-purpose digital I/O with port interrupt and mappable secondary function
Default mapping: USCI_B0 SPI slave in/master out; USCI_B0 I2C data
General-purpose digital I/O with port interrupt and mappable secondary function
Default mapping: USCI_B0 SPI slave out/master in; USCI_B0 I2C clock
P2.3/P2MAP3
20
H4
I/O
General-purpose digital I/O with port interrupt and mappable secondary function
Default mapping: USCI_B0 clock input/output; USCI_A0 SPI slave transmit enable
General-purpose digital I/O with port interrupt and mappable secondary function
Default mapping: USCI_A0 UART transmit data; USCI_A0 SPI slave in/master out
P2.5/P2MAP5
22
K1
I/O
General-purpose digital I/O with port interrupt and mappable secondary function
Default mapping: USCI_A0 UART receive data; USCI_A0 slave out/master in
General-purpose digital I/O with port interrupt and mappable secondary function
P2.6/P2MAP6/R03
23
K2
I/O
Default mapping: no secondary function
Input/output port of lowest analog LCD voltage (V5)
General-purpose digital I/O with port interrupt and mappable secondary function
Default mapping: no secondary function
External reference voltage input for regulated LCD voltage
Input/output port of third most positive analog LCD voltage (V3 or V4)
DVCC1
DVSS1
VCORE
(2)
I/O
(1)
DESCRIPTION
P5.6/ADC12CLK/DMAE0
P2.1/P2MAP1
18
H2
I/O
P2.2/P2MAP2
19
J1
I/O
P2.4/P2MAP4
21
J2
I/O
P2.7/P2MAP7/LCDREF/R13
24
L2
I/O
25
26
27
28
L1
M1
M2
L3
I/O
Digital power supply
Digital ground supply
Regulated core power supply (internal use only, no external current loading)
General-purpose digital I/O
Input/output port of second most positive analog LCD voltage (V2)
P5.2/R23
LCDCAP/R33
COM0
P5.3/COM1/S42
29
30
31
M3
J4
L4
I/O
O
I/O
LCD capacitor connection
Input/output port of most positive analog LCD voltage (V1)
CAUTION:
LCDCAP/R33 must be connected to DV
SS
if not used.
LCD common output COM0 for LCD backplane
General-purpose digital I/O
LCD common output COM1 for LCD backplane
LCD segment output S42
General-purpose digital I/O
LCD common output COM2 for LCD backplane
LCD segment output S41
P5.4/COM2/S41
32
M4
I/O
P5.5/COM3/S40
33
J5
I/O
General-purpose digital I/O
LCD common output COM3 for LCD backplane
LCD segment output S40
(2)
VCORE is for internal use only. No external current loading is possible. VCORE should only be connected to the recommended
capacitor value, C
VCORE
.
11
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