MSP430F673x
MSP430F672x
SLAS731A – DECEMBER 2011 – REVISED APRIL 2012
Pin Designation, MSP430F673xIPN
PJ.2/ADC10CLK/TMS
PJ.1/MCLK/TDI/TCLK
RST/NMI/SBWTDIO
PJ.0/SMCLK/TDO
PJ.3/ACLK/TCK
TEST/SBWTCK
P5.5/S10
P5.3/S12
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61
SD0P0
SD0N0
SD1P0
SD1N0
SD2P0
SD2N0
VREF
AVSS
AVCC
VASYS
P1.0/PM_TA0.0/VeREF-/A2
P1.1/PM_TA0.1/VeREF+/A1
P1.2/PM_UCA0RXD/PM_UCA0SOMI/A0
P1.3/PM_UCA0TXD/PM_UCA0SIMO/R03
AUXVCC2
AUXVCC1
VDSYS
DVCC
DVSS
VCORE
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
PN PACKAGE
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
DVSS
DVSYS
P5.1/S14
P5.0/S15
P4.7/S16
P4.6/S17
P4.5/S18
P4.4/S19
P4.3/S20
P4.2/S21
P4.1/S22
P4.0/S23
P3.7/PM_SD2DIO/S24
P3.6/PM_SD1DIO/S25
P3.5/PM_SD0DIO/S26
P3.4/PM_SDCLK/S27
P3.3/PM_TA0.2/S28
P3.2/PM_TACLK/PM_RTCCLK/S29
P3.1/PM_TA2.1/S30/BSL_RX
P3.0/PM_TA2.0/S31/BSL_TX
20
41
21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
XOUT
XIN
COM0
COM1
COM2
COM3
P2.6/PM_TA1.0/S33
P2.1/PM_UCB0SIMO/PM_UCB0SDA/COM7/S38
P2.3/PM_UCA2TXD/PM_UCA2SIMO/S36
P1.6/PM_UCA0CLK/COM4
P1.7/PM_UCB0CLK/COM5
P2.4/PM_UCA1CLK/S35
P1.5/PM_UCA1TXD/PM_UCA1SIMO/R23
P1.4/PM_UCA1RXD/PM_UCA1SOMI/LCDREF/R13
P2.0/PM_UCB0SOMI/PM_UCB0SCL/COM6/S39
P2.2/PM_UCA2RXD/PM_UCA2SOMI/S37
P2.5/PM_UCA2CLK/S34
P2.7/PM_TA1.1/S32
AUXVCC3
LCDCAP/R33
NOTE: The secondary digital functions on Ports P1, P2, and P3 are fully mappable. The pin designation shows the default
mapping. See
for details.
NOTE: The pins VDSYS and DVSYS must be connected externally on board for proper device operation.
CAUTION: The LCDCAP/R33 pin must be connected to DVSS if not used.
Copyright © 2011–2012, Texas Instruments Incorporated
P5.2/S13
P5.4/S11
P6.7/S0
P6.6/S1
P6.5/S2
P6.4/S3
P6.3/S4
P6.2/S5
P6.1/S6
P6.0/S7
P5.7/S8
P5.6/S9
7
TI [ TEXAS INSTRUMENTS ]
