MSP430F673x
MSP430F672x
SLAS731A – DECEMBER 2011 – REVISED APRIL 2012
Table 5. Terminal Functions, MSP430F67xxIPZ
TERMINAL
NAME
SD0P0
SD0N0
SD1P0
SD1N0
SD2P0
SD2N0
VREF
AVSS
AVCC
VASYS
NO.
PZ
1
2
3
4
5
6
7
8
9
10
I
I
I
I
I
I
I
SD24_B positive analog input for converter 0
(2)
SD24_B negative analog input for converter 0
(2)
SD24_B positive analog input for converter 1
(2)
SD24_B negative analog input for converter 1
(2)
SD24_B positive analog input for converter 2
(2)
(not available on F672x devices)
SD24_B negative analog input for converter 2
(2)
(not available on F672x devices)
SD24_B external reference voltage
Analog ground supply
Analog power supply
Analog power supply selected between AVCC, AUXVCC1, AUXVCC2. Connect
recommended capacitor value of C
VSYS
(see
I/O
General-purpose digital I/O
Analog input A5 - 10-bit ADC
General-purpose digital I/O
Analog input A4 - 10-bit ADC
General-purpose digital I/O
Analog input A3 - 10-bit ADC
General-purpose digital I/O with port interrupt and mappable secondary function
Default mapping: Timer TA0 CCR0 capture: CCI0A input, compare: Out0 output
P1.0/PM_TA0.0/VeREF-/A2
14
I/O
Negative terminal for the ADC's reference voltage for an external applied reference
voltage
Analog input A2 - 10-bit ADC
General-purpose digital I/O with port interrupt and mappable secondary function
P1.1/PM_TA0.1/VeREF+/A1
15
I/O
Default mapping: Timer TA0 CCR1 capture: CCI1A input, compare: Out1 output
Positive terminal for the ADC's reference voltage for an external applied reference
voltage
Analog input A1 - 10-bit ADC
P1.2/PM_UCA0RXD/
PM_UCA0SOMI/A0
16
I/O
General-purpose digital I/O with port interrupt and mappable secondary function
Default mapping: eUSCI_A0 UART receive data; eUSCI_A0 SPI slave out/master in
Analog input A0 - 10-bit ADC
General-purpose digital I/O with port interrupt and mappable secondary function
17
18
19
20
21
22
(4)
I/O
(1)
DESCRIPTION
P9.1/A5
11
P9.2/A4
12
I/O
P9.3/A3
13
I/O
P1.3/PM_UCA0TXD/
PM_UCA0SIMO/R03
AUXVCC2
AUXVCC1
VDSYS
(3)
DVCC
DVSS
VCORE
XIN
(1)
(2)
(3)
(4)
I/O
Default mapping: eUSCI_A0 UART transmit data; eUSCI_A0 SPI slave in/master out
Input/output port of lowest analog LCD voltage (V5)
Auxiliary power supply AUXVCC2
Auxiliary power supply AUXVCC1
Digital power supply selected between DVCC, AUXVCC1, AUXVCC2. Connect
recommended capacitor value of C
VSYS
(see
Digital power supply
Digital ground supply
Regulated core power supply (internal use only, no external current loading)
23
24
I
Input terminal for crystal oscillator
I = input, O = output
It is recommended to short unused analog input pairs and connect them to analog ground.
The pins VDSYS and DVSYS must be connected externally on board for proper device operation.
VCORE is for internal use only. No external current loading is possible. VCORE should only be connected to the recommended
capacitor value, C
VCORE
.
9
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