MSP430L092
MSP430C09x
SLAS673 – SEPTEMBER 2010
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Interrupt Vector Addresses
The interrupt vectors and the power-up start address are located in the address range 0FFFFh to 0FFE0h. The
vector contains the 16-bit address of the appropriate interrupt-handler instruction sequence.
Table 4. Interrupt Sources, Flags, and Vectors
INTERRUPT SOURCE
System Reset
Power-Up
External Reset
Watchdog
System NMI
Vacant memory access
User NMI
NMI
Timer1_A3
Timer1_A3
Watchdog Timer_A Interval Timer Mode
A-Pool
I/O Port P1
Timer0_A3
Timer0_A3
I/O Port P2
Reserved
INTERRUPT FLAG
SYSTEM
INTERRUPT
Reset
WORD ADDRESS
PRIORITY
WDTIFG
(1)
0x0FFFE
15, highest
SVMIFG, VMAIFG
(1)
NMIIFG
(1) (2)
TA1CCR0 CCIFG0
(3)
TA1CCR1 CCIFG1
(1) (3)
WDTIFG
CxIFG
P1IFG.0 to P1IFG.6
(1) (3)
(3)
(Non)maskable
(Non)maskable
Maskable
Maskable
Maskable
Maskable
Maskable
Maskable
Maskable
Maskable
0x0FFFC
0x0FFFA
0x0FFF8
0x0FFF6
0x0FFF4
0x0FFF2
0x0FFF0
0x0FFEE
0x0FFEC
0x0FFEA
0x0FFE8
⋮
0x0FFE0
14
13
12
11
10
9
8
7
6
5
4
⋮
0
TA0CCR0 CCIFG0
P2IFG.0 to P2IFG.3
Reserved
(4)
TA0CCR1 CCIFG1
(1) (3)
(1) (3)
(1)
(2)
(3)
(4)
Multiple source flags
A reset is generated if the CPU tries to fetch instructions from within peripheral space or vacant memory space. (Non)maskable: the
individual interrupt-enable bit can disable an interrupt event, but the general-interrupt enable cannot disable it.
Interrupt flags are located in the module.
Reserved interrupt vectors at addresses are not used in this device and can be used for regular program code if necessary. To maintain
compatibility with other devices, it is recommended to reserve these locations.
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