MSP430F563x
SLAS650B
–
JUNE 2010
–
REVISED AUGUST 2011
SHORT-FORM DESCRIPTION
CPU
The MSP430 CPU has a 16-bit RISC architecture
that is highly transparent to the application. All
operations, other than program-flow instructions, are
performed as register operations in conjunction with
seven addressing modes for source operand and four
addressing modes for destination operand.
The CPU is integrated with 16 registers that provide
reduced
instruction
execution
time.
The
register-to-register operation execution time is one
cycle of the CPU clock.
Four of the registers, R0 to R3, are dedicated as
program counter, stack pointer, status register, and
constant generator, respectively. The remaining
registers are general-purpose registers.
Peripherals are connected to the CPU using data,
address, and control buses, and can be handled with
all instructions.
Program Counter
Stack Pointer
Status Register
Constant Generator
General-Purpose Register
General-Purpose Register
General-Purpose Register
General-Purpose Register
General-Purpose Register
General-Purpose Register
General-Purpose Register
General-Purpose Register
General-Purpose Register
General-Purpose Register
General-Purpose Register
General-Purpose Register
PC/R0
SP/R1
SR/CG1/R2
CG2/R3
R4
R5
R6
R7
R8
R9
R10
R11
R12
R13
R14
R15
Instruction Set
The instruction set consists of the original 51
instructions with three formats and seven address
modes and additional instructions for the expanded
address range. Each instruction can operate on word
and byte data.
shows examples of the three
types of instruction formats;
shows the
address modes.
Table 4. Instruction Word Formats
INSTRUCTION WORD FORMAT
Dual operands, source-destination
Single operands, destination only
Relative jump, un/conditional
EXAMPLE
ADD
CALL
JNE
R4,R5
R8
OPERATION
R4 + R5
→
R5
PC
→
(TOS), R8
→
PC
Jump-on-equal bit = 0
Table 5. Address Mode Descriptions
ADDRESS MODE
Register
Indexed
Symbolic (PC relative)
Absolute
Indirect
Indirect auto-increment
Immediate
(1)
S = source, D = destination
S
(1)
+
+
+
+
+
+
+
D
(1)
+
+
+
+
SYNTAX
MOV Rs,Rd
MOV X(Rn),Y(Rm)
MOV EDE,TONI
MOV
&MEM, &TCDAT
MOV @Rn,Y(Rm)
MOV @Rn+,Rm
MOV #X,TONI
MOV @R10,Tab(R6)
MOV @R10+,R11
MOV #45,TONI
EXAMPLE
MOV R10,R11
MOV 2(R5),6(R6)
OPERATION
R10
→
R11
M(2+R5)
→
M(6+R6)
M(EDE)
→
M(TONI)
M(MEM)
→
M(TCDAT)
M(R10)
→
M(Tab+R6)
M(R10)
→
R11
R10 + 2
→
R10
#45
→
M(TONI)
14
Copyright
©
2010–2011, Texas Instruments Incorporated
TI [ TEXAS INSTRUMENTS ]
