MSP430F563x
SLAS650B
–
JUNE 2010
–
REVISED AUGUST 2011
DESCRIPTION
The Texas Instruments MSP430 family of ultralow-power microcontrollers consists of several devices featuring
different sets of peripherals targeted for various applications. The architecture, combined with five low power
modes is optimized to achieve extended battery life in portable measurement applications. The device features a
powerful 16-bit RISC CPU, 16-bit registers, and constant generators that contribute to maximum code efficiency.
The digitally controlled oscillator (DCO) allows wake-up from low-power modes to active mode in 3
µs
(typical).
The MSP430F563x series are microcontroller configurations with a high performance 12-bit analog-to-digital
(A/D) converter, comparator, two universal serial communication interfaces (USCI), USB 2.0, hardware multiplier,
DMA, four 16-bit timers, real-time clock module with alarm capabilities, and up to 74 I/O pins.
Typical applications for this device include analog and digital sensor systems, digital motor control, remote
controls, thermostats, digital timers, hand-held meters, etc.
Family members available are summarized in
Table 1. Family Members
USCI
Device
Flash
(KB)
SRAM
(KB)
(1)
Timer_A
(2)
Timer_B
(3)
Channel A:
UART/IrDA/
SPI
2
2
2
2
2
2
2
2
2
Channel B:
SPI/I
2
C
2
2
2
2
2
2
2
2
2
ADC12_A
(Ch)
12 ext /
4 int
12 ext /
4 int
12 ext /
4 int
12 ext /
4 int
12 ext /
4 int
12 ext /
4 int
-
-
-
DAC12_A
(Ch)
Comp_B
(Ch)
I/O
Package
Type
100 PZ,
113 ZQW
100 PZ,
113 ZQW
100 PZ,
113 ZQW
100 PZ,
113 ZQW
100 PZ,
113 ZQW
100 PZ,
113 ZQW
100 PZ,
113 ZQW
100 PZ,
113 ZQW
100 PZ,
113 ZQW
MSP430F5638
MSP430F5637
MSP430F5636
MSP430F5635
MSP430F5634
MSP430F5633
MSP430F5632
MSP430F5631
MSP430F5630
256
192
128
256
192
128
256
192
128
16 + 2
16 + 2
16 + 2
16 + 2
16 + 2
16 + 2
16 + 2
16 + 2
16 + 2
5, 3, 3
5, 3, 3
5, 3, 3
5, 3, 3
5, 3, 3
5, 3, 3
5, 3, 3
5, 3, 3
5, 3, 3
7
7
7
7
7
7
7
7
7
2
2
2
-
-
-
-
-
-
12
12
12
12
12
12
12
12
12
74
74
74
74
74
74
74
74
74
(1)
(2)
(3)
The additional 2 KB USB SRAM that is listed can be used as general purpose SRAM when USB is not in use.
Each number in the sequence represents an instantiation of Timer_A with its associated number of capture compare registers and PWM
output generators available. For example, a number sequence of 3, 5 would represent two instantiations of Timer_A, the first
instantiation having 3 and the second instantiation having 5 capture compare registers and PWM output generators, respectively.
Each number in the sequence represents an instantiation of Timer_B with its associated number of capture compare registers and PWM
output generators available. For example, a number sequence of 3, 5 would represent two instantiations of Timer_B, the first
instantiation having 3 and the second instantiation having 5 capture compare registers and PWM output generators, respectively.
2
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2010–2011, Texas Instruments Incorporated
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