REMOTE 16-BIT I
2
C AND SMBus, LOW-POWER I/O EXPANDER
WITH INTERRUPT OUTPUT AND CONFIGURATION REGISTERS
SCPS129E – AUGUST 2005 – REVISED FEBRUARY 2007
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Interrupt (INT) Output
An interrupt is generated by any rising or falling edge of the port inputs in the input mode. After time, t
iv
, the
signal INT is valid. Resetting the interrupt circuit is achieved when data on the port is changed to the original
setting or data is read from the port that generated the interrupt or in a Stop event. Resetting occurs in the read
mode at the acknowledge (ACK) bit or not acknowledge (NACK) bit after the falling edge of the SCL signal. In a
Stop event, INT is cleared after the rising edge of SDA. Interrupts that occur during the ACK or NACK clock
pulse can be lost (or be very short) due to the resetting of the interrupt during this pulse. Each change of the
I/Os after resetting is detected and is transmitted as INT.
Reading from or writing to another device does not affect the interrupt circuit, and a pin configured as an output
cannot cause an interrupt. Changing an I/O from an output to an input may cause a false interrupt to occur, if the
state of the pin does not match the contents of the Input Port register. Because each 8-bit port is read
independently, the interrupt caused by port 0 is not cleared by a read of port 1, or vice versa.
INT has an open-drain structure and requires a pullup resistor to V
CC
.
Bus Transactions
Data is exchanged between the master and the PCA9535 through write and read commands.
Writes
Data is transmitted to the PCA9535 by sending the device address and setting the least-significant bit to a logic
0 (see
for device address). The command byte is sent after the address and determines which register
receives the data that follows the command byte.
The eight registers within the PCA9535 are configured to operate as four register pairs. The four pairs are Input
Ports, Output Ports, Polarity Inversions, and Configurations. After sending data to one register, the next data
byte is sent to the other register in the pair (see
and
For example, if the first byte is sent to
Output Port 1 (register 3), the next byte is stored in Output Port 0 (register 2).
There is no limitation on the number of data bytes sent in one write transmission. In this way, each 8-bit register
may be updated independently of the other registers.
SCL
1
2
3
4
5
6
7
8
9
Command Byte
Data to Port 0
Data to Port 1
Slave Address
SDA
S
0
1
0
0
A2 A1 A0
0
A
0
0
0
0
0
0
1
0
A 0.7
Acknowledge
From Slave
Data 0
0.0
A 1.7
Acknowledge
From Slave
Data 1
1.0
A
P
Start Condition
Write to Port
R/W
Acknowledge
From Slave
Data Out from Port 0
t
pv
Data Out from Port 1
Data Valid
t
pv
Figure 6. Write to Output Port Registers
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