Reset
common +5V power supply for all three power pins. If
separate supplies are used without a common connection,
the delta between the supplies during ramp-up time must be
less than 0.3V. An application circuit to avoid a power-on
latch-up condition is shown in Figure 15.
The PCM1727 has both an internal power-on reset circuit
and the RSTB pin (pin 10) which accepts an external forced
reset by RSTB = LOW. For internal power-on reset, initial-
ize (reset) is done automatically at power on VDD > 2.2V
(typ). During internal reset = LOW, the output of the DAC
is invalid and the analog outputs are forced to VCC/2. Figure
13 illustrates the timing of the internal power-on reset.
The PCM1727 accepts an external forced reset when
RSTB = L. When RSTB = L, the output of the DAC is invalid
and the analog outputs are forced to VCC/2 after internal
initialization (1024 system clocks count after RSTB = H.)
Figure 14 illustrates the timing of the RSTB reset pin.
Digital
Power Supply
Analog
Power Supply
For system applications, the power-up time of the internal
PLL circuit to provide a stable system clock output, is
approximately 1024 system clocks plus a 15ms transient
time.
VDD
VCP VCA
AGND
DGND
POWER SUPPLY
CONNECTIONS
FIGURE 15. Latch-up Prevention Circuit.
The PCM1727 has three power supply connections: digital
(VDD), analog (VCA), and PLL (VCP). Each connection also
has a separate ground return pin. It is acceptable to use a
2.6V
2.2V
1.8V
VCC/VDD
Reset
Reset Removal
Internal Reset
SCKO2 Clock
1024 system (SCKO2) clocks
FIGURE 13. Internal Power-On Reset Timing.
RSTB
50% of VDD
(1)
tRST
Reset
Reset Removal
Internal Reset
SCKO2 Clock
1024 system (SCKO2) clocks
NOTE: (1) tRST = 20ns min
FIGURE 14. RSTB-Pin Reset Timing.
PCM1727
SBAS077A
13
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