BYPASSING POWER SUPPLIES
The combined oversampling rate of the delta-sigma modu-
lator and the internal 8X interpolation filter is 48fS for a
384fS system clock. The theoretical quantization noise per-
formance of the 5-level delta-sigma modulator is shown in
Figure 17.
The power supplies should be bypassed as close as
possible to the unit. Refer to Figure 18 for optimal values of
bypass capacitors. It is also recommended to include a
0.1µF ceramic capacitor in parallel with the 10µF tantalum
capacitor.
THEORY OF OPERATION
The delta-sigma section of the PCM1727 is based on a
5-level amplitude quantizer and a 3rd-order noise shaper.
This section converts the oversampled input data to 5-level
delta-sigma format.
AC-3 APPLICATION CIRCUIT
A typical application for the PCM1727 is AC-3 5.1 channel
audio decoding and playback. This circuit uses the PCM1727
to develop the audio system clock from the 27MHz video
clock, with the SCKO2 pin used to drive the AC-3 decoder
and two PCM1720 units, the non-PLL version of the
PCM1723 and PCM1727.
A block diagram of the 5-level delta-sigma modulator is
shown in Figure 16. This 5-level delta-sigma modulator has
the advantage of stability and clock jitter sensitivity over the
typical one-bit (2 level) delta-sigma modulator.
+
+
+
+
+
+
Z–1
Z–1
Z–1
In
8fS
18-Bit
–
–
+
+
+
5-level Quantizer
4
3
2
1
0
Out
48fS (384fS)
FIGURE 16. 5-Level ∆Σ Modulator Block Diagram.
3rd ORDER ∆Σ MODULATOR
20
0
–20
–40
–60
–80
–100
–120
–140
–160
0
5
10
15
20
25
Frequency (kHz)
FIGURE 17. Quantization Noise Spectrum.
PCM1727
14
SBAS077A
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