PTH12030W/L
www.ti.com
SLTS211F–MAY 2003–REVISED FEBRUARY 2007
ELECTRICAL CHARACTERISTICS
TA = 25°C, VI = 12 V, VO = 3.3 V, CI= 560 µF, CO = 0 µF, and IO = IOmax (unless otherwise stated)
PTH12030L
CHARACTERISTICS
CONDITIONS
60°C, 200 LFM airflow
MIN
0
TYP
MAX
26(1)
26(1)
13.8
±2(2)
UNIT
IO
Output current
A
25°C, natural convection
0
VI
Input voltage range
Set-point voltage tolerance
Temperature variation
Line regulation
Over lO range
10.2
V
VO tol
%VO
%VO
mV
mV
%VO
V
∆Regtemp
∆Regline
∆Regload
∆Regtot
∆Vadj
–40°C < TA < 85°C
±0.5
±5
Over VI range
Load regulation
Over IO range
±5
Total output variation
VO adjust range
Includes set-point, line, load, –40°C ≤ TA ≤ 85 °C
Over VI range
±3(2)
0.8
1.8
RSET = 130 Ω
VO = 1.8 V
VO = 1.5 V
VO = 1.2 V
VO = 1 V
89%
87%
85%
83%
80%
15
RSET = 3.57 kΩ
RSET = 12.1 kΩ
RSET = 32.4 kΩ
RSET = open cct
η
Efficiency
IO = 18 A
VO = 0.8 V
VO ripple (peak-to-peak)
Overcurrent threshold
20-MHz bandwidth
mVPP
A
IO trip
ttr
Reset, followed by auto-recovery
50
Recovery Time
50
µS
1 A/µs load step,
50 to 100% Iomax, CO= 330 µF
Transient response
∆Vtr
VO over/undershoot
150
±5
-8(3)
mV
%
Margin up/down adjust
Margin control (pins
12&13)
Margin input current, Pin to GND
µA
IIL track
Track input current (pin 11) Pin to GND
–0.13(4)
mA
V/ms
dVtrack/dt
Track slew rate capability
CO≤ CO (max)
1
VI increasing
9.5
8.5
10
UVLO
Undervoltage lockout
V
V
VI decreasing
8.8
2.5
Input high voltage (VIH)
Input low voltage (VIL)
Input low current (IIL)
Input standby current
Switching frequency
Referenced to GND
Referenced to GND
Pin 4 to GND
Open(5)
0.5
Inhibit
control
(pin4)
–0.2
0.5
10
mA
mA
kHz
µF
II inh
fs
Inhibit (pin 4) to GND, track (pin 11) VI
Over VI and IO ranges
475
560(6)
575
675
CI
External input capacitance
nonceramic
ceramic
0
330(7) 7150(8)
300
Capacitance value
µF
External output
capacitance
CO
0
Equivalent series resistance (nonceramic)
4(9)
3
mΩ
106 Hr
MTBF
Reliability
Bellcore TR-332, 50% stress, TA= 40°C, ground benign
(1) See SOA curves or consult factory for appropriate derating.
(2) The set-point voltage tolerance is affected by the tolerance and stability of RSET. The stated limit is unconditionally met if RSET has a
tolerance of 1%, with 100 ppm/°C (or better) temperature stability.
(3) A small, low-leakage (<100 nA) MOSFET is recommended to control this pin. The open-circuit voltage is less than 1 Vdc.
(4) A low-leakage (<100 nA), open-drain device, such as MOSFET or voltage supervisor IC, is recommended to control this pin.
(5) This control pin is pulled up to an internal 5-V source. To avoid risk of damage to the module, do not apply an external voltage greater
than 7 V. If it is left open-circuit, the module operates when input power is applied. A small, low-leakage (<100 nA) MOSFET or
open-drain/collector voltage supervisor IC is recommended for control. For further information, see the application information section.
(6) A 560 µF electrolytic input capacitor, rated for a minimum of 500 mArms of ripple current is required for proper operation.
(7) An external output capacitor is not required for basic operation. Adding 330 µF of distributed capacitance at the load improves the
transient response.
(8) This is the calculated maximum. The minimum ESR limitation often results in a lower value. See the application information section.
(9) This is the typical ESR for all the electrolytic (non-ceramic) ouput capacitance. Use 7 mΩ as the minimum when using max-ESR values
to calculate.
4
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