RM48L930
RM48L730
RM48L530
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SPNS176–SEPTEMBER 2011
5.8.2 I2C I/O Timing Specifications
Table 5-14. I2C Signals (SDA and SCL) Switching Characteristics(1)
Parameter
Standard Mode
Fast Mode
Unit
MIN
MAX
MIN
MAX
tc(I2CCLK)
Cycle time, Internal Module clock for I2C,
prescaled from VCLK
75.2
149
75.2
149
ns
tc(SCL)
Cycle time, SCL
10
2.5
0.6
ms
ms
tsu(SCLH-SDAL)
Setup time, SCL high before SDA low (for a
repeated START condition)
4.7
th(SCLL-SDAL)
Hold time, SCL low after SDA low (for a repeated
START condition)
4
0.6
ms
tw(SCLL)
Pulse duration, SCL low
4.7
4
1.3
0.6
100
0
ms
ms
ns
tw(SCLH)
Pulse duration, SCL high
tsu(SDA-SCLH)
th(SDA-SCLL)
Setup time, SDA valid before SCL high
250
0
Hold time, SDA valid after SCL low (for I2C bus
devices)
3.45(2)
0.9
ms
tw(SDAH)
Pulse duration, SDA high between STOP and
START conditions
4.7
4.0
1.3
0.6
0
ms
ms
tsu(SCLH-SDAH)
tw(SP)
Setup time, SCL high before SDA high (for STOP
condition)
Pulse duration, spike (must be suppressed)
Capacitive load for each bus line
50
ns
(3)
Cb
400
400
pF
(1) The I2C pins SDA and SCL do not feature fail-safe I/O buffers. These pins could potentially draw current when the device is powered
down.
(2) The maximum th(SDA-SCLL) for I2C bus devices has only to be met if the device does not stretch the low period (tw(SCLL)) of the SCL
signal.
(3) Cb = The total capacitance of one bus line in pF.
SDA
tw(SDAH)
tsu(SDA-SCLH)
tw(SP)
tw(SCLL)
tr(SCL)
tsu(SCLH-SDAH)
tw(SCLH)
SCL
tc(SCL)
th(SCLL-SDAL)
tf(SCL)
th(SCLL-SDAL)
tsu(SCLH-SDAL)
th(SDA-SCLL)
Stop
Start
Repeated Start
Stop
Figure 5-8. I2C Timings
Copyright © 2011, Texas Instruments Incorporated
Peripheral Information and Electrical Specifications
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