SPNS176
–
SEPTEMBER 2011
1.4
Functional Block Diagram
DMMSYNC
DMMDATA[15:0]
TRACECTL
ETMDATA[31:0]
RTPSYNC
RTPDATA[15:0]
TRACECLKIN
TRACECLK
Color Legend for Power Domains
Core/RAM
always on
DMMCLK
DMMnENA
RTPnENA
RTPCLK
Core
RAM
#1
#2
#3
#4
3M
Flash
with
ECC
64K
64K
64K
64K
256K
RAM
with
ECC
#1
#2
#3
RTP
POM
DMM
ETM-R4
HTU1
HTU2
USB Host
#5
DMA
Dual Cortex-R4F
CPUs in Lockstep
Switched Central Resource Switched Central Resource Switched Central Resource
Main Cross Bar: Arbitration and Prioritization Control
64 KB Flash
for EEPROM
Emulation
with ECC
CRC
Switched Central Resource
Peripheral Central Resource Bridge
SYS
IOMM
USB Slaves
EMIF_nWAIT
EMIF_CLK
EMIF_CKE
EMIF_nCS[4:2]
EMIF_nCS[0]
EMIF_ADDR[21:0]
EMIF_BA[1:0]
EMIF_DATA[15:0]
EMIF_nDQM[1:0]
EMIF_nOE
EMIF_nWE
EMIF_nRAS
EMIF_nCAS
EMIF_nRW
USB1.OverCurrent
USB1.RCV
USB1.VM
USB1.VP
USB1.PortPower
USB1.SPEED
USB1.SUSPEND
USB1.TXDAT
USB1.TXEN
USB1.TXSE0
USB2.OverCurrent
USB2.RCV
USB2.VM
USB2.VP
USB2.PortPower
USB2.SPEED
USB2.SUSPEND
USB2.TXDAT
USB2.TXEN
USB2.TXSE0
USB_FUNC.GZO
USB_FUNC.PUENO
USB_FUNC.PUENON
USB_FUNC.RXDI
USB_FUNC.RXDMI
USB_FUNC.RXDPI
USB_FUNC.SE0O
USB_FUNC.SUSPENDO
USB_FUNC.TXDO
USB_FUNC.VBUSI
nPORRST
nRST
ECLK
nERROR
CAN1_RX
CAN1_TX
CAN2_RX
CAN2_TX
CAN3_RX
CAN3_TX
MIBSPI1_CLK
MIBSPI1_SIMO[1:0]
MIBSPI1_SOMI[1:0]
MIBSPI1_nCS[5:0]
MIBSPI1_nENA
SPI2_CLK
SPI2_SIMO
SPI2_SOMI
SPI2_nCS[1:0]
SPI2_nENA
MIBSPI3_CLK
MIBSPI3_SIMO
MIBSPI3_SOMI
MIBSPI3_nCS[5:0]
MIBSPI3_nENA
SPI4_CLK
SPI4_SIMO
SPI4_SOMI
SPI4_nCS0
SPI4_nENA
MIBSPI5_SIMO[3:0]
MIBSPI5_SOMI[3:0]
MIBSPI5_nCS[3:0]
MIBSPI5_nENA
LIN_RX
LIN_TX
SCI_RX
SCI_TX
ESM
PMM
DCAN1
DCAN2
DCAN3
VIM
EMIF
Host
RTI
MibSPI1
DCC1
SPI2
DCC2
MibSPI3
Device
SPI4
MibADC1
ADREFLO
AD1EVT
AD1IN[7:0]
AD1IN[23:8]
VCCAD
VSSAD
ADREFHI
AD2IN[15:0]
MibADC2
ADREFLO
AD2EVT
VCCAD
VSSAD
ADREFHI
N2HET1
N2HET1[31:0]
N2HET2
N2HET2[15:0]
N2HET2[18,16
GIO
GIOA[7:0]
GIOB[7:0]
I2C
I2C_SDA
I2C_SCL
MibSPI5
LIN
SCI
Figure 1-1. Functional Block Diagram
Copyright
©
2011, Texas Instruments Incorporated
RM48Lx30 16/32-Bit RISC Flash Microcontroller
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