SPNS176
–
SEPTEMBER 2011
1
RM48Lx30 16/32-Bit RISC Flash Microcontroller
2
...............................................................
1.1
Features
..............................................
1.2
Applications
..........................................
1.3
Description
...........................................
1.4
Functional Block Diagram
............................
1.1
Device Configuration
.................................
Device Package and Terminal Functions
.........
2.2
PGE QFP Package Pinout (144-Pin)
...............
2.3
ZWT BGA Package Ball-Map (337 Ball Grid Array)
4.5
4.6
4.7
4.8
4.9
4.10
4.11
4.12
4.13
4.14
4.15
4.16
4.17
4.18
4.19
4.20
4.21
.............
Clocks
..............................................
Clock Monitoring
....................................
Glitch Filters
........................................
Device Memory Map
................................
Flash Memory
......................................
Tightly-Coupled RAM Interface Module
............
ARM
©
Cortex-R4F™ CPU Information
Parity Protection for Accesses to peripheral RAMs
3
......................................................
2.4
Terminal Functions
.................................
Device Operating Conditions
.......................
3.1
3.2
3.3
3.4
3.5
3.6
3.7
3.8
3.9
3.10
Absolute Maximum Ratings Over Operating
Free-Air Temperature Range,
......................
Device Recommended Operating Conditions
......
Switching Characteristics over Recommended
Operating Conditions for Clock Domains
...........
Wait States Required
...............................
Power Consumption Over Recommended
Operating Conditions
...............................
Input/Output Electrical Characteristics Over
Recommended Operating Conditions
..............
......................................................
On-Chip SRAM Initialization and Testing
...........
External Memory Interface (EMIF)
.................
Vectored Interrupt Manager
........................
DMA Controller
.....................................
Real Time Interrupt Module
........................
Error Signaling Module
.............................
Reset / Abort / Error Sources
.......................
Digital Windowed Watchdog
........................
Debug Subsystem
.................................
Peripheral Legend
.................................
Multi-Buffered 12bit Analog-to-Digital Converter
.....................................................
5
Peripheral Information and Electrical
Specifications
.........................................
5.1
5.2
5.3
5.4
5.5
5.6
5.7
5.8
5.9
PRODUCT PREVIEW
......................
Input Timings
.......................................
Output Timings
.....................................
Low-EMI Output Buffers
............................
Output Buffer Drive Strengths
4
System Information and Electrical Specifications
.............................................................
4.1
Device Power Domains
.............................
4.2
Voltage Monitor Characteristics
....................
4.3
Power Sequencing and Power On Reset
..........
4.4
Warm Reset (nRST)
................................
....................
Enhanced High-End Timer (N2HET)
..............
Controller Area Network (DCAN)
..................
Local Interconnect Network Interface (LIN)
.......
Serial Communication Interface (SCI)
............
Inter-Integrated Circuit (I2C)
......................
General-Purpose Input/Output
Multi-Buffered / Standard Serial Peripheral Interface
.....................................................
6
Mechanical Data
6.1
6.2
......................................
Thermal Data
......................................
Packaging Information
............................
6
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2011, Texas Instruments Incorporated
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