RM48L930
RM48L730
RM48L530
www.ti.com
SPNS176–SEPTEMBER 2011
An additional use of this module is to measure the frequency of a selectable clock source, using the input
clock as a reference, by counting the pulses of two independent clock sources. Counter 0 generates a
fixed-width counting window after a preprogrammed number of pulses. Counter 1 generates a fixed-width
pulse (1 cycle) after a pre-programmed number of pulses. This pulse sets as an error signal if counter 1
does not reach 0 within the counting window generated by counter 0.
4.7.3.1 Features
Takes two different clock sources as input to two independent counter blocks.
•
•
One of the clock sources is the known-good, or reference clock; the second clock source is the "clock
under test."
•
•
Each counter block is programmable with initial, or seed values.
The counter blocks start counting down from their seed values at the same time; a mismatch from the
expected frequency for the clock under test generates an error signal which is used to interrupt the
CPU.
4.7.3.2 Mapping of DCC Clock Source Inputs
Table 4-16. DCC1 Counter 0 Clock Sources
CLOCK SOURCE [3:0]
CLOCK NAME
oscillator (OSCIN)
high frequency LPO
test clock (TCK)
others
0x5
0xA
Table 4-17. DCC1 Counter 1 Clock Sources
KEY [3:0]
CLOCK SOURCE [3:0]
CLOCK NAME
N2HET1[31]
others
-
0x0
Main PLL free-running clock output
reserved
0x1
0x2
low frequency LPO
high frequency LPO
flash HD pump oscillator
EXTCLKIN1
0xA
0x3
0x4
0x5
0x6
EXTCLKIN2
0x7
ring oscillator
0x8 - 0xF
VCLK
Table 4-18. DCC2 Counter 0 Clock Sources
CLOCK SOURCE [3:0]
CLOCK NAME
others
0xA
oscillator (OSCIN)
test clock (TCK)
Table 4-19. DCC2 Counter 1 Clock Sources
KEY [3:0]
others
0xA
CLOCK SOURCE [3:0]
CLOCK NAME
N2HET2[0]
Reserved
VCLK
-
00x0 - 0x7
0x8 - 0xF
Copyright © 2011, Texas Instruments Incorporated
System Information and Electrical Specifications
63
Submit Documentation Feedback
focus.ti.com: RM48L930 RM48L730 RM48L530
TI [ TEXAS INSTRUMENTS ]
