RM48L930
RM48L730
RM48L530
SPNS176–SEPTEMBER 2011
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4.13.2 On-Chip SRAM Auto Initialization
This microcontroller allows some of the on-chip memories to be initialized via the Memory Hardware
Initialization mechanism in the System module. This hardware mechanism allows an application to
program the memory arrays with error detection capability to a known state based on their error detection
scheme (odd/even parity or ECC).
The MINITGCR register enables the memory initialization sequence, and the MSINENA register selects
the memories that are to be initialized.
For more information on these registers see the RM48x Technical Reference Manual (SPNU481).
The mapping of the different on-chip memories to the specific bits of the MSINENA registers is shown in
Table 4-26.
Table 4-26. Memory Initialization
ADDRESS RANGE
CONNECTING MODULE
MSINENA REGISTER BIT #
BASE ADDRESS
0x08000000
0x08010000
0x08020000
0x08030000
0xFF0A0000
0xFF0C0000
0xFF0E0000
0xFF1A0000
0xFF1C0000
0xFF1E0000
0xFF3A0000
0xFF3E0000
0xFF440000
0xFF460000
0xFF4C0000
0xFF4E0000
0xFFF80000
0xFFF82000
0xFC520000
ENDING ADDRESS
0x0800FFFF
0x0801FFFF
0x0802FFFF
0x0803FFFF
0xFF0BFFFF
0xFF0DFFFF
0xFF0FFFFF
0xFF1BFFFF
0xFF1DFFFF
0xFF1FFFFF
0xFF3BFFFF
0xFF3FFFFF
0xFF57FFFF
0xFF47FFFF
0xFF4DFFFF
0xFF4FFFFF
0xFFF80FFF
0xFFF82FFF
0xFC521FFF
RAM (PD#1)
RAM (RAM_PD#1)
RAM (RAM_PD#2)
RAM (RAM_PD#3)
MIBSPI5 RAM
MIBSPI3 RAM
MIBSPI1 RAM
DCAN3 RAM
DCAN2 RAM
DCAN1 RAM
MIBADC2 RAM
MIBADC1 RAM
N2HET2 RAM
N2HET1 RAM
HET TU2 RAM
HET TU1 RAM
DMA RAM
0(1)
0(1)
0(1)
0(1)
12(2)
11(2)
7(2)
10
6
5
14
8
15
3
16
4
1
VIM RAM
2
Reserved
n/a
(1) The TCM RAM wrapper has separate control bits to select the RAM power domain that is to be auto-initialized.
(2) The MibSPIx modules perform an initialization of the transmit and receive RAMs as soon as the multi-buffered mode is enabled. This is
independent of whether the application chooses to initialize the MibSPIx RAMs using the system module auto-initialization method.
78
System Information and Electrical Specifications
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