SN65MLVD2DRBTG4 参数 Datasheet PDF下载

SLLS767 – NOVEMBER 2006

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CLOCK INPUT

VA - VB

1/fo

Period Jitter

IDEAL

OUTPUT

VOH

VCC /2

VOL

1/fo

INPUTS

VA - VB

VCM

0.4 V

1.0 V

VA

PRBS INPUT

ACTUAL

OUTPUT

V OH

VCC/2

VOL

tc(n)

tjit(per) = | tc(n) - 1/fo |

Cycle to Cycle Jitter

V

B

Peak to Peak Jitter

VOH

OUTPUT

VCC/2

VOL

t jit(pp)

OUTPUT

VOH

VCC /2

VOL

tc(n)

tc(n+1)

tjit(cc) = | tc(n) - tc(n+1)|

A.

B.

C.

D.

All input pulses are supplied by the Agilent 81250 Parallel BERT Stimulus System with plug-in E4832A.

The cycle-to-cycle jitter measurement is made on a TEK TDS6604 running TDSJIT3 application software

Period jitter is measured using a 125-MHz 50

±

1% duty cycle clock input.

Deterministic jitter and random jitter are measured using a 250-Mbps 2

15-1

PRBS input

Figure 4. Receiver Jitter Measurement Waveforms

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