SN74AVCH16T245
16 BIT DUAL SUPPLY BUS TRANSCEIVER
WITH CONFIGURABLE VOLTAGE TRANSLATION AND 3 STATE OUTPUTS
SCES587A − AUGUST 2004 − REVISED OCTOBER 2004
D
Control Inputs V
IH
/V
IL
Levels Are
D
D
D
D
D
D
D
D
Referenced to V
CCA
Voltage
V
CC
Isolation Feature − If Either V
CC
Input
Is at GND, Both Ports Are in the
High-Impedance State
Overvoltage-Tolerant Inputs/Outputs Allow
Mixed-Voltage-Mode Data Communications
Fully Configurable Dual-Rail Design Allows
Each Port to Operate Over the Full 1.2-V to
3.6-V Power-Supply Range
I
off
Supports Partial-Power-Down Mode
Operation
I/Os Are 4.6-V Tolerant
Bus Hold on Data Inputs Eliminates the
Need for External Pullup/Pulldown
Resistors
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
ESD Protection Exceeds JESD 22
− 8000-V Human-Body Model (A114-A)
− 200-V Machine Model (A115-A)
− 1000-V Charged-Device Model (C101)
DGG OR DGV PACKAGE
(TOP VIEW)
description/ordering information
24
25
This 16-bit noninverting bus transceiver uses two
separate configurable power-supply rails. The
SN74AVCH16T245 is optimized to operate with
V
CCA
/V
CCB
set at 1.4 V to 3.6 V. It is operational with V
CCA
/V
CCB
as low as 1.2 V. The A port is designed to track
V
CCA
. V
CCA
accepts any supply voltage from 1.2 V to 3.6 V. The B port is designed to track V
CCB
. V
CCB
accepts
any supply voltage from 1.2 V to 3.6 V. This allows for universal low-voltage bidirectional translation between
any of the 1.2-V, 1.5-V, 1.8-V, 2.5-V, and 3.3-V voltage nodes.
1DIR
1B1
1B2
GND
1B3
1B4
V
CCB
1B5
1B6
GND
1B7
1B8
2B1
2B2
GND
2B3
2B4
V
CCB
2B5
2B6
GND
2B7
2B8
2DIR
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
1OE
1A1
1A2
GND
1A3
1A4
V
CCA
1A5
1A6
GND
1A7
1A8
2A1
2A2
GND
2A3
2A4
V
CCA
2A5
2A6
GND
2A7
2A8
2OE
The SN74AVCH16T245 is designed for asynchronous communication between data buses. The device
transmits data from the A bus to the B bus or from the B bus to the A bus, depending on the logic level at the
direction-control (DIR) input. The output-enable (OE) input can be used to disable the outputs so the buses are
effectively isolated.
The SN74AVCH16T245 is designed so that the control pins (1DIR, 2DIR, 1OE, and 2OE) are supplied by V
CCA
.
ORDERING INFORMATION
TA
PACKAGE†
TSSOP − DGG
−40°C to 85°C
TVSOP − DGV
VFBGA − GQL
VFBGA − ZQL (Pb-free)
Tape and reel
Tape and reel
Tape and reel
ORDERABLE
PART NUMBER
SN74AVCH16T245GR
SN74AVCH16T245VR
SN74AVCH16T245KR
74AVCH16T245ZQLR
TOP-SIDE
MARKING
AVCH16T245
WJ245
WJ245
† Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright
2004, Texas Instruments Incorporated
POST OFFICE BOX 655303
•
DALLAS, TEXAS 75265
1
TI [ TEXAS INSTRUMENTS ]
