SN74F175
QUADRUPLE D-TYPE FLIP-FLOP
WITH CLEAR
SDFS058B – D293, MARCH 1987 – REVISED MAY 2002
PARAMETER MEASUREMENT INFORMATION
7V
From Output
Under Test
CL
(see Note A)
Test
Point
500
Ω
From Output
Under Test
CL
(see Note A)
500
Ω
S1
500
Ω
Open
TEST
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open Collector
LOAD CIRCUIT FOR
TOTEM-POLE OUTPUTS
LOAD CIRCUIT FOR
3-STATE AND OPEN-DRAIN OUTPUTS
3V
Timing Input
tw
3V
Input
1.5 V
1.5 V
0V
1.5 V
VOLTAGE WAVEFORMS
PULSE DURATION
3V
Input
tPLH
In-Phase
Output
tPHL
Out-of-Phase
Output
1.5 V
1.5 V
1.5 V
1.5 V
0V
tPHL
VOH
1.5 V
VOL
tPLH
VOH
1.5 V
VOL
Output
Waveform 2
S1 at GND
(see Note B)
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
3V
1.5 V
tPZL
Output
Waveform 1
S1 at 7 V
(see Note B)
tPZH
1.5 V
0V
tPLZ
1.5 V
tPHZ
VOH – 0.3 V
VOH
≈0
V
≈3.5
V
VOL + 0.3 V
VOL
Data Input
tsu
1.5 V
1.5 V
0V
th
3V
1.5 V
0V
S1
Open
7V
Open
7V
Output
Control
1.5 V
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR
≤
1 MHz, ZO = 50
Ω,
tr
≤
2.5 ns, tf
≤
2.5 ns,
duty cycle = 50%.
D. The outputs are measured one at a time with one input transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
4
POST OFFICE BOX 655303
•
DALLAS, TEXAS 75265