SLES257 – SEPTEMBER 2010
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7.3
Error Status Register (0x02)
Note that the error bits are sticky bits that are not cleared by the hardware. This means that the software
must clear the register (write zeroes) and then read them to determine if there are any persistent errors.
Table 7-3. Error Status Register Format
D7
1
–
–
–
–
0
D6
–
1
–
–
–
0
D5
–
–
1
–
–
0
D4
–
–
–
1
–
0
D3
–
–
–
–
1
0
D2
–
–
–
–
–
0
D1
–
–
–
–
–
0
D0
–
–
–
–
–
0
PLL phase lock error
PLL auto lock error
SCLK error
LRCLK error
Frame slip
No errors
FUNCTION
7.4
System Control Register 1 (0x03)
Bits D5, D2, D1, and D0 are
Don't Care.
Table 7-4. System Control Register 1 Format
D7
0
1
–
–
–
–
D6
–
–
–
–
–
–
D5
D4
–
–
0
1
–
–
D3
–
–
D2
D1
D0
PWM high pass disabled
PWM high pass enabled
Function
Soft unmute on recovery from clock error
Hard unmute on recovery from clock error
1
0
PSVC Hi-Z enable
PSVC Hi-Z disable
7.5
System Control Register 2 (0x04)
Bits D3 and D2 are
Don't Care.
Table 7-5. System Control Register 2 Format
D7
0
–
–
–
–
–
–
–
–
–
D6
–
0
1
–
–
–
–
–
–
–
D5
–
–
–
0
1
–
–
–
–
–
–
D4
–
–
–
–
–
0
1
–
–
–
–
D3
D2
D1
–
–
–
–
–
–
–
0
0
1
1
D0
–
–
–
–
–
–
–
0
1
0
1
Reserved
Function
PWM automute detection enabled
PWM automute detection disabled
8-Ch device input detection automute enabled
8-Ch device input detection automute disabled
Unmute threshold 6 dB over input threshold
Unmute threshold equal to input threshold
No de-emphasis
De-emphasis for Fs = 32 kHz
De-emphasis for Fs = 44.1 kHz
De-emphasis for Fs = 48 kHz
7.6
Channel Configuration Control Registers (0x05–0x0C)
Channels 1, 2, 3, 4, 5, 6, 7, and 8 are mapped into 0x05, 0x06, 0x07, 0x08, 0x09, 0x0A, 0x0B, and 0x0C,
respectively.
Bit D0 is
Don't Care.
74
Serial-Control Interface Register Definitions
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