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SLES263 – NOVEMBER 2010
AUDIO SPECIFICATION (PBTL)
Audio performance is recorded as a chipset consisting of a TAS5518 PWM processor (modulation index limited to 97.7%)
and a TAS5631B power stage. PCB and system configurations are in accordance with recommended guidelines. Audio
frequency = 1 kHz, PVDD_X = 50 V, GVDD_X = 12 V, R
L
= 2
Ω,
f
S
= 384 kHz, R
OC
= 22 kΩ, T
C
= 75°C;
output filter: L
DEM
= 7
mH,
C
DEM
= 1
mF,
MODE = 101-00, unless otherwise noted.
PARAMETER
TEST CONDITIONS
R
L
= 2
Ω,
10%, THD+N, clipped input signal
R
L
= 3
Ω,
10%, THD+N, clipped input signal
P
O
Power output per channel
R
L
= 4
Ω,
10%, THD+N, unclipped input signal
R
L
= 2
Ω,
1% THD+N, unclipped input signal
R
L
= 3
Ω,
1% THD+N, unclipped input signal
R
L
= 4
Ω,
1% THD+N, unclipped input signal
THD+N
V
n
SNR
DNR
P
idle
(1)
(2)
Total harmonic distortion + noise
Output integrated noise
Signal-to-noise ratio
Dynamic range
Power dissipation due to idle losses (I
PVDD_X
)
(1)
MIN
TYP MAX
600
400
300
480
310
230
0.03%
170
103
103
3.7
UNIT
W
1W
A-weighted, TAS5518 modulator
A-weighted, TAS5518 modulator
A-weighted, input level –60 dBFS using
TAS5518 modulator
P
O
= 0, 4 channels switching
(2)
mV
dB
dB
W
SNR is calculated relative to 1% THD-N output level.
Actual system idle losses are affected by core losses of output inductors.
ELECTRICAL CHARACTERISTICS
PVDD_X = 50V, GVDD_X = 12 V, VDD = 12V, T
C
(case temperature) = 75°C, f
S
= 384 kHz, unless otherwise specified.
PARAMETER
INTERNAL VOLTAGE REGULATOR AND CURRENT CONSUMPTION
VREG
VI_CM
I
VDD
I
GVDD_x
Voltage regulator, only used as reference
node, VREG
Analog comparator reference node, VI_CM
VDD supply current
Gate-supply current per half-bridge
Operating, 50% duty cycle
Idle, reset mode
50% duty cycle
Reset mode
50% duty cycle without output filter or
load
Reset mode, no switching
OUTPUT-STAGE MOSFETs
Drain-to-source resistance, low side (LS)
R
DS(on)
Drain-to-source resistance, high side (HS)
T
J
= 25°C, excludes metallization
resistance,
GVDD = 12 V
60
60
100
100
mΩ
mΩ
VDD = 12 V
3
1.5
3.3
1.75
22.5
22.5
12.5
1.5
19.5
750
3.6
1.9
V
V
mA
mA
mA
mA
TEST CONDITIONS
MIN
TYP MAX
UNIT
I
PVDD_x
Half-bridge idle current
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