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SLAS052G – MARCH 1992 – REVISED JANUARY 2006
OPERATING CHARACTERISTICS (continued)
over recommended operating free-air temperature range, V
CC
= V
ref+
= 4.5 V to 5.5 V, I/O CLOCK frequency = 2.1 MHz
(unless otherwise noted)
TEST
CONDITIONS
TLC1542C, I, or Q
E
ZS
Zero-scale error, see
(3)
MIN
TYP
(1)
MAX
±1
±1
±1
±1
±1
±1
±1
±1
±1
UNIT
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
See
See
See
See
See
See
(4)
(4)
(4)
(4)
(4)
(4)
TLC1543C, I, or Q
TLC1542M
TLC1542C, I, or Q
E
FS
Full-scale error, see
(3)
TLC1543C, I, or Q
TLC1542M
TLC1542C, I, or Q
Total unadjusted error, see
(5)
TLC1543C, I, or Q
TLC1542M
ADDRESS = 1011
512
0
1023
Self-test output code, see
and
(6)
ADDRESS = 1100
ADDRESS = 1101
See timing
diagrams
See timing
diagrams and
See timing
diagrams and
See
See
See
See
See
See
See
See
See
See
t
conv
Conversion time
21
21
+10 I/O
CLOCK
periods
6
10
240
70
240
100
1.3
150
300
300
300
300
9
µs
t
c
Total cycle time (access, sample, and conversion)
(7)
µs
I/O CLOCK
periods
ns
ns
ns
ns
µs
ns
ns
ns
ns
ns
µs
t
acq
t
v
t
d(I/O-DATA)
t
d(I/O-EOC)
t
d(EOC-DATA)
t
PZH
, t
PZL
t
PHZ
, t
PLZ
t
r(EOC)
t
f(EOC)
t
r(DATA)
t
f(DATA)
t
d(I/O-CS)
(3)
(4)
(5)
(6)
(7)
(8)
Channel acquisition time (sample)
Valid time, DATA OUT remains valid after I/O CLOCK↓
Delay time, I/O CLOCK↓ to DATA OUT valid
Delay time, tenth I/O CLOCK↓ to EOC↓
Delay time, EOC↑ to DATA OUT (MSB)
Enable time, CS↓ to DATA OUT (MSB driven)
Disable time, CS↑ to DATA OUT (high impedance)
Rise time, EOC
Fall time, EOC
Rise time, data bus
Fall time, data bus
Delay time, tenth I/O CLOCK↓ to CS↓ to abort
conversion (see Note
(8)
)
(7)
Zero-scale error is the difference between 0000000000 and the converted output for zero input voltage; full-scale error is the difference
between 1111111111 and the converted output for full-scale input voltage.
Analog input voltages greater than that applied to REF+ convert as all ones (1111111111), while input voltages less than that applied to
REF- convert as all zeros (0000000000). The device is functional with reference voltages down to 1 V (V
ref+
-V
ref-
); however, the
electrical specifications are no longer applicable.
Total unadjusted error comprises linearity, zero-scale, and full-scale errors.
Both the input address and the output codes are expressed in positive logic.
I/O CLOCK period = 1/(I/O CLOCK frequency) (see Figure 6)
Any transitions of CS are recognized as valid only if the level is maintained for a setup time plus two falling edges of the internal clock
(1.425
µs)
after the transition.
10
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