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TLC5970RHPR 参数 Datasheet PDF下载

TLC5970RHPR图片预览
型号: TLC5970RHPR
PDF下载: 下载PDF文件 查看货源
内容描述: 3通道, 12位, PWM LED驱动器,降压型DC / DC转换器和差分信号接口 [3-Channel, 12-Bit, PWM LED Driver with Buck DC/DC Converter and Differential Signal Interface]
分类和应用: 显示驱动器转换器驱动程序和接口接口集成电路
文件页数/大小: 48 页 / 635 K
品牌: TI [ TEXAS INSTRUMENTS ]
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www.ti.com
SBVS140 – MARCH 2010
THERMAL INFORMATION
TLC5970
THERMAL METRIC
(1)
q
JA
q
JC(top)
q
JB
y
JT
y
JB
q
JC(bottom)
(1)
(2)
(3)
(4)
(5)
(6)
(7)
Junction-to-ambient thermal resistance
(2)
Junction-to-case(top) thermal resistance
Junction-to-board thermal resistance
(4)
(5)
(6)
(3)
RHP
28
26.7
11.7
5.3
0.4
5.2
1.6
UNITS
Junction-to-top characterization parameter
°C/W
Junction-to-board characterization parameter
Junction-to-case(bottom) thermal resistance
(7)
For more information about traditional and new thermal metrics, see the
IC Package Thermal Metrics
application report,
The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, High-K board, as
specified in JESD51-7, in an environment described in JESD51-2a.
The junction-to-case(top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDEC-standard
test exists, but a close description can be found in the ANSI SEMI standard G30-88.
The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB
temperature, as described in JESD51-8.
The junction-to-top characterization parameter,
y
JT
, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining
q
JA
, using a procedure described in JESD51-2a (sections 6 and 7).
The junction-to-board characterization parameter,
y
JB
estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining
q
JA
, using a procedure described in JESD51-2a (sections 6 and 7).
The junction-to-case(bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific
JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
DISSIPATION RATINGS
PACKAGE
HTSSOP-32
with PowerPAD soldered
(1) (2)
HTSSOP-32
with PowerPAD unsoldered
(2) (3)
QFN-28
bottom side heat sink soldered
(4)
(1)
(2)
(3)
(4)
DERATING FACTOR
ABOVE T
A
= +25°C
42.5 mW/°C
22.5 mW/°C
33.2 mW/°C
POWER RATING
T
A
< +25°C
5318 mW
2820 mW
4149 mW
POWER RATING
T
A
= +70°C
3403 mW
1805 mW
2655 mW
POWER RATING
T
A
= +85°C
2765 mW
1466 mW
2157 mW
With PowerPAD soldered onto copper area on printed circuit board (PCB); 2-oz. copper. For more information, see
(available for download at
Product preview device.
With PowerPAD not soldered onto copper area on PCB.
The package thermal impedance is calculated in accordance with JESD51-5.
Copyright © 2010, Texas Instruments Incorporated
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