www.ti.com
SLVS412D – DECEMBER 2001 – REVISED FEBRUARY 2007
PIN ASSIGNMENTS
PWP PACKAGE
(TOP VIEW)
AGND
VSENSE
COMP
PWRGD
BOOT
PH
PH
PH
PH
PH
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
RT
SYNC
SS/ENA
VBIAS
VIN
VIN
VIN
PGND
PGND
PGND
TERMINAL FUNCTIONS
TERMINAL
NAME
AGND
BOOT
COMP
PGND
PH
PWRGD
RT
SS/ENA
SYNC
VBIAS
VIN
VSENSE
NO.
1
5
3
11–13
6–10
4
20
18
19
17
14–16
2
DESCRIPTION
Analog ground. Return for compensation network/output divider, slow-start capacitor, VBIAS capacitor, RT resistor
and SYNC pin. Make PowerPAD connection to AGND.
Bootstrap input. 0.022-µF to 0.1-µF low-ESR capacitor connected from BOOT to PH generates floating drive for
the high-side FET driver.
Error amplifier output. Connect compensation network from COMP to VSENSE.
Power ground. High current return for the low-side driver and power MOSFET. Connect PGND with large copper
areas to the input and output supply returns, and negative terminals of the input and output capacitors.
Phase input/output. Junction of the internal high and low-side power MOSFETs, and output inductor.
Power good open drain output. High when VSENSE
≥
90% V
ref
, otherwise PWRGD is low. Note that output is low
when SS/ENA is low or internal shutdown signal active.
Frequency setting resistor input. Connect a resistor from RT to AGND to set the switching frequency, f
s
.
Slow-start/enable input/output. Dual function pin which provides logic input to enable/disable device operation and
capacitor input to externally set the start-up time.
Synchronization input. Dual function pin which provides logic input to synchronize to an external oscillator or pin
select between two internally set switching frequencies. When used to synchronize to an external signal, a resistor
must be connected to the RT pin.
Internal bias regulator output. Supplies regulated voltage to internal circuitry. Bypass VBIAS pin to AGND pin with
a high quality, low ESR 0.1-µF to 1.0-µF ceramic capacitor.
Input supply for the power MOSFET switches and internal bias regulator. Bypass VIN pins to PGND pins close to
device package with a high quality, low ESR 1-µF to 10-µF ceramic capacitor.
Error amplifier inverting input.
5
TI [ TEXAS INSTRUMENTS ]
