SLVSAB1D – JUNE 2011 – REVISED JULY 2012
ELECTRICAL CHARACTERISTICS (continued)
V
IN
= 14 V, T
J
= –40ºC to 150ºC (unless otherwise noted)
PARAMETER
(3)
TEST CONDITIONS
V
IN-RIPPLE
= 0.5 Vpp, I
OUT
= 200 mA, frequency = 100
Hz, V
OUT
= 5 V and V
OUT
= 3.3 V
V
IN-RIPPLE
= 0.5 Vpp, I
OUT
= 200 mA, frequency = 150
kHz, V
OUT
= 5 V and V
OUT
= 3.3 V
I
OL
= 5 mA
Reset pulled to VOUT through a 5-kΩ resistor
V
OUT
powered up above internally set tolerance,
V
OUT
= 5 V
V
OUT
powered up above internally set tolerance,
V
OUT
= 3.3 V
V
OUT
falling below internally set tolerance,
V
OUT
= 5 V
V
OUT
falling below internally set tolerance,
V
OUT
= 3.3 V
C
DLY
= 100 pF
C
DLY
= 100 nF
C
DLY
not connected, V
OUT
= 5 V and V
OUT
= 3.3 V
MIN
TYP
60
MAX
UNIT
PSRR
Power-supply ripple
rejection
dB
30
Reset (nRST Pin)
V
OL
I
OH
Reset pulled low
Leakage current
0.4
1
4.5
4.65
3.07
4.5
4.65
3.07
300
300
250
5.5
µs
ms
µs
µs
4.77
V
4.77
V
V
µA
V
TH(POR)
Power-on-reset threshold
UV
THRES
Reset threshold
t
POR (2)
t
POR-PRESET
t
DEGLITCH
Power-on-reset delay
Internally preset
Power-on-reset delay
Reset deglitch time
Threshold to release nRST
high
Delay capacitor
charging current
Delay capacitor
discharging current
Voltage reference
Logic output low level
Leakage current
Reset Delay (RDELAY Pin)
V
TH(RDELAY)
I
DLY
I
OL
Voltage at RDELAY pin is ramped up
0.75
Voltage at RDELAY pin = 1 V
5
3
1
3.3
1.25
V
µA
mA
Current Voltage Reference (ROSC Pin)
V
ROSC
V
OL
I
OH
0.95
I
OL
= 5 mA
WD_FLT/WD_FLG pulled to V
OUT
through 5-kΩ
resistor
1
1.05
0.4
1
V
V
µA
Watchdog Fault/ Flag Output ( WD_FLT/ WD_FLAG Pin)
Watchdog Enable Input (nWD_EN Pin)
V
IL
V
IH
V
IL
V
IH
t
WD
Logic input low level
Logic input high level
Logic input low level
Logic input high level
Watchdog window duration
Tolerance of watchdog
period using external
resistor
Default watchdog period
Minimum pulse width for
resetting watch dog timer
5.25 V < V
DD
< 3 V
R
OSC
= 10 kΩ ± 1%
R
OSC
= 20kΩ ± 1%
Excludes tolerance of R
OSC
(external resistor connected to ROSC pin)
External resistor not connected, ROSC pin is floating
or open
–10%
108
164
1.65
2.5
10
20
10%
254
ms
µs
5.25 V < V
DD
< 3 V
2.5
0.8
0.8
V
Watchdog Input Pulse (WD Pin)
V
ms
t
WD-tol
t
WD-DEFAULT
t
WD-HOLD
(3)
Specified by design - not tested.
4
Copyright © 2011–2012, Texas Instruments Incorporated
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