SLES135E
–
FEBRUARY 2005
–
REVISED APRIL 2011
3-84
3-85
3-86
3-87
3-88
3-89
3-90
3-91
3-92
3-93
3-94
3-95
3-96
3-97
3-98
3-99
3-100
3-101
3-102
3-103
3-104
3-105
3-106
3-107
3-108
3-109
3-110
3-111
3-112
3-113
3-114
3-115
3-116
3-117
3-118
3-119
3-120
3-121
3-122
3-123
3-124
3-125
3-126
3-127
3-128
3-129
3-130
3-131
..........................................................................................................
AGC Increment Speed
..........................................................................................................
AGC Increment Delay
...........................................................................................................
Analog Output Control 1
........................................................................................................
Chip ID MSB
.....................................................................................................................
Chip ID LSB
......................................................................................................................
RAM Version LSB
...............................................................................................................
Color PLL Speed Control
.......................................................................................................
3DYC Luma Coring LSB
........................................................................................................
3DYC Chroma Coring LSB
.....................................................................................................
3DYC Luma/Chroma Coring MSB
............................................................................................
3DYC Luma Gain
................................................................................................................
3DYC Chroma Gain
.............................................................................................................
3DYC Signal Quality Gain
......................................................................................................
3DYC Signal Quality Coring
....................................................................................................
IF Compensation Control
.......................................................................................................
IF Differential Gain Control
.....................................................................................................
IF Low Frequency Gain Control
...............................................................................................
IF High Frequency Gain Control
...............................................................................................
Weak Signal High Threshold
...................................................................................................
Weak Signal High Threshold
...................................................................................................
Status Request
..................................................................................................................
3DYC NTSC VCR Threshold
..................................................................................................
3DYC PAL VCR Threshold
.....................................................................................................
Vertical Line Count
..............................................................................................................
AGC Decrement Delay
.........................................................................................................
VDP TTX Filter and Mask
......................................................................................................
VDP TTX Filter Control
.........................................................................................................
VDP FIFO Word Count
.........................................................................................................
VDP FIFO Interrupt Threshold
.................................................................................................
VDP FIFO Reset
.................................................................................................................
VDP FIFO Output Control
......................................................................................................
VDP Line Number Interrupt
....................................................................................................
VDP Pixel Alignment
............................................................................................................
VDP Line Start
...................................................................................................................
VDP Line Stop
...................................................................................................................
VDP Global Line Mode
.........................................................................................................
VDP Full Field Enable
..........................................................................................................
VDP Full Field Mode
............................................................................................................
Interlaced/Progressive Status
..................................................................................................
VBUS Data Access with No VBUS Address Increment
....................................................................
VBUS Data Access with VBUS Address Increment
........................................................................
VDP FIFO Read Data
...........................................................................................................
VBUS Address
...................................................................................................................
Interrupt Raw Status 0
..........................................................................................................
Interrupt Raw Status 1
..........................................................................................................
Interrupt Status 0
................................................................................................................
Interrupt Status 1
................................................................................................................
F-Bit and V-Bit Control
List of Tables
7
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2005–2011, Texas Instruments Incorporated
TI [ TEXAS INSTRUMENTS ]
