SLUS646J
–
NOVEMBER 2005
–
REVISED JULY 2011
OPEN LOOP TEST CIRCUIT
R
CST
+ 5V
37.4 kΩ
See Note
C
CST
560 pF
See Note
C
FB
47 pF
V
CS
I
CS
3 CS
VDD 6
I
DD
UCC28600
1 SS STATUS 8
C
SS
3.3 nF
2 FB
OVP 7
R
OVP
500
Ω
STATUS
I
OVP
V
FB
V
OVP
V
DD
4 GND
GND
OUT 5
C
DD
100 nF
R
OUT
10
Ω
C
OUT
1.0 nF
V
OUT
C
BIAS
1
µF
NOTE
R
CST
and C
CST
are not connected for maximum and minimum duty cycle tests, current
sense tests and power limit tests.
BLOCK DIAGRAM/TYPICAL APPLICATION
C
BULK
R
SU
R
VDD
C
VDD
R
OVP1
OVP
R
OVP2
7
VDD
6
UCC28600
REF
On-Chip
Thermal
Shutdown
STATUS
8
5.0
VREF
Fault Logic
REF_OK
OVR_T
STATUS
SS_DIS
SS_OVR
UVLO
LOAD_OVP
LINE_OVP
CS
BURST
RUN
QR DETECT
____
LOAD_OVP OUT
LINE_OVP
CS
BURST
QR_DONE
VDD
UVLO
+
26 V
13/8 V
SS
C
SS
OSCILLATOR
1
SS_OVR
OSC_CL
+
GREEN MODE
OSC_CL
FB
REF
GAIN = 1/2.5
20 kW
FB_CLAMP
PL
1.2 V
Modulation
Comparison
CS
3
R
PL
R
CS
1.5R
R
+
400 mV
GND
CLR
RUN
QR_DONE
CLK
REF
D
SET
Q
5
OUT
Q
Feedback
FB
2
+
4
Copyright
©
2005–2011, Texas Instruments Incorporated
5
TI [ TEXAS INSTRUMENTS ]
