SCPS216A – JULY 2009 – REVISED FEBRAURY 2010
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8.23 Isochronous Transmit Interrupt Event Register
The isochronous transmit interrupt event set/clear register reflects the interrupt state of the isochronous
transmit contexts. An interrupt is generated on behalf of an isochronous transmit context if an
OUTPUT_LAST* command completes and its interrupt bits are set to 1. Upon determining that the
isochTx (bit 6) interrupt has occurred in the interrupt event register at OHCI offset 80h/84h (see
software can check this register to determine which context caused the interrupt. The
interrupt bits are set to 1 by an asserting edge of the corresponding interrupt signal, or by writing a 1b in
the corresponding bit in the set register. The only mechanism to clear a bit in this register is to write a 1b
to the corresponding bit in the clear register. See
for a complete description of the register
contents.
OHCI register
offset:
90h set register
94h clear register (returns the contents of the isochronous transmit interrupt
event register bit-wise ANDed with the isochronous transmit interrupt
mask register when read)
Register type:
Default value:
BIT NUMBER
RESET STATE
BIT NUMBER
RESET STATE
31
0
15
0
30
0
14
0
Read/Set/Clear, Read only
0000 00XXh
29
0
13
0
28
0
12
0
27
0
11
0
26
0
10
0
25
0
9
0
24
0
8
0
23
0
7
X
22
0
6
X
21
0
5
X
20
0
4
X
19
0
3
X
18
0
2
X
17
0
1
X
16
0
0
X
Table 8-17. Isochronous Transmit Interrupt Event Register Description
BIT
31-8
7
6
5
4
3
2
1
0
FIELD NAME
RSVD
isoXmit7
isoXmit6
isoXmit5
isoXmit4
isoXmit3
isoXmit2
isoXmit1
isoXmit0
TYPE
R
RSC
RSC
RSC
RSC
RSC
RSC
RSC
RSC
DESCRIPTION
Reserved. Bits 31-8 return 0000h when read.
Isochronous transmit context 7 caused the interrupt event register bit 6 (isochTx) interrupt.
Isochronous transmit context 6 caused the interrupt event register bit 6 (isochTx) interrupt.
Isochronous transmit context 5 caused the interrupt event register bit 6 (isochTx) interrupt.
Isochronous transmit context 4 caused the interrupt event register bit 6 (isochTx) interrupt.
Isochronous transmit context 3 caused the interrupt event register bit 6 (isochTx) interrupt.
Isochronous transmit context 2 caused the interrupt event register bit 6 (isochTx) interrupt.
Isochronous transmit context 1 caused the interrupt event register bit 6 (isochTx) interrupt.
Isochronous transmit context 0 caused the interrupt event register bit 6 (isochTx) interrupt.
150
1394 OHCI Memory-Mapped Register Space
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