SCPS216A – JULY 2009 – REVISED FEBRAURY 2010
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10.2.2 Power-Up Reset
To ensure proper operation of the XIO2221 PHY section, the RESET terminal must be asserted low for a
minimum of 2 ms from the time that DVDD, AVDD, and PLLVDD power reaches the minimum required
supply voltage and the input clock is valid. If a fundamental-mode crystal is used rather than an oscillator,
the start-up time parameter may be set to zero. When using a passive capacitor on the RESET terminal to
generate a power-on-reset signal, the minimum reset time is ensured if the value of the capacitor satisfies
the following equation (the value must be no smaller than approximately 0.1
mF):
C
min
= (0.0077 T) + 0.085 + (external_oscillator_start-up_time 0.05)
Where:
C
min
= Minimum capacitance on RESET terminal (F)
T = V
DD
ramp time, 10% to 90% (ms)
external_oscillator_start-up_time = Time from power applied to external oscillator until oscillator outputs a
valid clock (ms)
10.2.3 Crystal Oscillator Selection
The XIO2221 is designed to use an external 98.304-MHz crystal oscillator connected to the XI terminal to
provide the reference clock. This clock, in turn, drives a PLL circuit that generates the various clocks
required for transmission and resynchronization of data at the S100 through S800 media data rates.
A variation of less than ±100 ppm from nominal for the media data rates is required by IEEE Std 1394.
Adjacent PHYs may, therefore, have a difference of up to 200 ppm from each other in their internal clocks,
and PHYs must be able to compensate for this difference over the maximum packet length. Larger clock
variations can cause resynchronization overflows or underflows, resulting in corrupted packet data.
For the XIO2221, the PCLK output can be used to measure the frequency accuracy and stability of the
internal oscillator and PLL from which it is derived. The frequency of the PCLK output must be within ±100
ppm of the nominal frequency of 98.304 MHz.
The following are some typical specifications for an oscillator used with the XIO2221, in order to achieve
the required frequency accuracy and stability:
• RMS jitter of 5 ps or less
• RMS phase-noise jitter of 1 ps or less over the range 12 kHz to 20 MHz or higher
• Frequency tolerance at 25°C: Total frequency variation for the complete circuit is ±100 ppm. A device
with ±30-ppm or ±50-ppm frequency tolerance is recommended for adequate margin.
• Frequency stability (over temperature and age): A device with ±30-ppm or ±50-ppm frequency stability
is recommended for adequate margin.
The total frequency variation must be kept below ±100 ppm from nominal, with some allowance for
error introduced by board and device variations. Trade-offs between frequency tolerance and stability
may be made, as long as the total frequency variation is less than ±100 ppm. For example, the
frequency tolerance of the crystal may be specified at 50 ppm and the temperature tolerance may be
specified at 30 ppm to give a total of 80-ppm possible variation due to the oscillator alone. Aging also
contributes to the frequency variation. It is strongly recommended that part of the verification process
for the design is to measure the frequency of the PCLK output of the PHY section. This should be
done using a frequency counter with an accuracy of six digits or better.
186
Physical Layer (PHY) Section
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