tm
TE
CH
T436416A
BLOCK DIAGRAM
I/O Control
LW E
Bank Select
D ata Input R egister
LD Q M
1M x 16
1M x 16
1M x 16
1M x 16
Row Decoder
Row Buffeer
Refresh Counter
Sense AM P
Output Buffer
D Qi
Address Register
C LK
A DD
LCBR
LRAS
Col. Buffer
C olum n D ecoder
Latency & Burst Length
LC K E
LR A S
LC BR
LW E
LC A S
Tim ing Register
Program m ing R egister
LW C BR
LD Q M
C LK
C KE
CS
R AS
C AS
WE
L(U)D QM
TM Technology Inc. reserves the right
P. 2
to change products or specifications without notice.
Publication Date: MAY. 2003
Revision: B