TMC2130 DATASHEET (Rev. 1.09 / 2017-MAY-15)
11
2.2 Signal Descriptions
Pin
QFN36 TQFP48
Type Function
CLK input. Tie to GND using short wire for internal clock
or supply external clock.
SPI chip select input (negative active) (SPI_MODE=1) or
CLK
1
2
3
4
5
2
3
4
5
7
DI
DI
CSN_CFG3
SCK_CFG2
SDI_CFG1
SDO_CFG0
(tpu) Configuration input (SPI_MODE=0) (tristate detection).
DI SPI serial clock input (SPI_MODE=1) or
(tpu) Configuration input (SPI_MODE=0) (tristate detection).
DI SPI data input (SPI_MODE=1) or
(tpu) Configuration input (SPI_MODE=0) (tristate detection).
DIO SPI data output (tristate) (SPI_MODE=1) or
(tpu) Configuration input (SPI_MODE=0) (tristate detection).
STEP
DIR
VCC_IO
6
7
8
8
9
10
DI
DI
STEP input
DIR input
3.3V to 5V IO supply voltage for all digital pins.
Do not connect. Leave open to ensure highest distance
for high voltage pins in TQFP package!
Pins 9 and 11 may be connected to GND or left open.
11, 14, 16,
18, 20, 22,
28, 41, 43,
45, 47
DNC
9
-
Mode selection input with pullup resistor. When tied low,
the chip is in standalone mode and pins have their CFG
functions. When tied high, the SPI interface is available
for control. Integrated pull-up resistor.
Unused pin, connect to GND for compatibility to future
versions.
DI
(pu)
SPI_MODE
N.C.
10
11
12
6, 31, 36
GNDP
OB1
12, 35 13, 48
Power GND. Connect to GND plane near pin.
Motor coil B output 1
Sense resistor connection for coil B. Place sense resistor
to GND near pin. An additional 100nF capacitor to GND
(GND plane) is recommended for best performance.
Motor coil B output 2
Motor supply voltage. Provide filtering capacity near pin
with short loop to nearest GNDP pin (respectively via GND
plane).
13
14
15
15
17
19
BRB
OB2
VS
16, 31 21, 40
DCO
17
23
24
DIO
dcStep ready output
dcStep enable input (SPI_MODE=1) - tie to GND for normal
operation (no dcStep) or
Configuration input (SPI_MODE=0) (tristate detection).
dcStep gating input for axis synchronization (SPI_MODE=1)
or
Configuration input (SPI_MODE=0) (tristate detection).
Diagnostics output DIAG0. Use external pull-up resistor
with 47k or less in open drain mode.
DI
(tpu)
DCEN_CFG4 18
DI
(tpu)
DCIN_CFG5
19
25
DIAG0
DIAG1
20
21
26
27
DIO
DIO
Diagnostics output DIAG1. Use external pull-up resistor
with 47k or less in open drain mode.
Enable input (SPI_MODE=1) or
configuration / Enable input (SPI_MODE=0) (tristate
detection).
DRV_ENN_
CFG6
DI
(tpu)
22
23
29
30
The power stage becomes switched off (all motor outputs
floating) when this pin becomes driven to a high level.
Analog reference voltage for current scaling (optional
mode) or reference current for use of internal sense
resistors
AIN_IREF
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