TMC260 and TMC261 DATASHEET (Rev. 2.05 / 2012-NOV-05)
15
6 SPI Interface
TMC260 and TMC261 require setting configuration parameters and mode bits through the SPI interface
before the motor can be driven. The SPI interface also allows reading back status values and bits.
6.1 Bus Signals
The SPI bus on the TMC260 and the TMC261 has four signals:
SCK
SDI
SDO
CSN
bus clock input
serial data input
serial data output
chip select input (active low)
The slave is enabled for an SPI transaction by a low on the chip select input CSN. Bit transfer is
synchronous to the bus clock SCK, with the slave latching the data from SDI on the rising edge of SCK
and driving data to SDO following the falling edge. The most significant bit is sent first. A minimum
of 20 SCK clock cycles is required for a bus transaction with the TMC260 and the TMC261.
If more than 20 clocks are driven, the additional bits shifted into SDI are shifted out on SDO after a
20-clock delay through an internal shift register. This can be used for daisy chaining multiple chips.
CSN must be low during the whole bus transaction. When CSN goes high, the contents of the internal
shift register are latched into the internal control register and recognized as a command from the
master to the slave. If more than 20 bits are sent, only the last 20 bits received before the rising edge
of CSN are recognized as the command.
6.2 Bus Timing
SPI interface is synchronized to the internal system clock, which limits the SPI bus clock SCK to half
of the system clock frequency. If the system clock is based on the on-chip oscillator, an additional
10% safety margin must be used to ensure reliable data transmission. All SPI inputs as well as the
ENN input are internally filtered to avoid triggering on pulses shorter than 20ns. Figure 6.1 shows the
timing parameters of an SPI bus transaction, and the table below specifies their values.
CSN
tCC
tCL
tCH
tCH
tCC
SCK
SDI
tDU
tDH
bit19
bit18
bit0
bit0
tDO
tZC
bit19
bit18
SDO
Figure 6.1 SPI Timing
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