TMC260 and TMC261 DATASHEET (Rev. 2.05 / 2012-NOV-05)
18
6.4.2 Read Response Overview
The table below shows the formats for the read response. The RDSEL parameter in the DRVCONF
register selects the format of the read response.
Bit
RDSEL=%00 RDSEL=%01 RDSEL=%10
19
18
17
16
15
14
13
12
11
10
9
MSTEP9
MSTEP8
MSTEP7
MSTEP6
MSTEP5
MSTEP4
MSTEP3
MSTEP2
MSTEP1
MSTEP0
-
SG9
SG8
SG7
SG6
SG5
SG4
SG3
SG2
SG1
SG0
-
SG9
SG8
SG7
SG6
SG5
SE4
SE3
SE2
SE1
SE0
-
8
-
-
-
7
STST
6
OLB
5
OLA
4
3
2
1
S2GB
S2GA
OTPW
OT
0
SG
6.5 Driver Control Register (DRVCTRL)
The format of the DRVCTRL register depends on the state of the SDOFF mode bit.
SPI Mode
SDOFF bit is set, the STEP/DIR interface is disabled, and DRVCTRL is the interface for
specifying the currents through each coil.
STEP/DIR Mode SDOFF bit is clear, the STEP/DIR interface is enabled, and DRVCTRL is a configuration
register for the STEP/DIR interface.
6.5.1 DRVCTRL Register in SPI Mode
DRVCTRL
Driver Control in SPI Mode (SDOFF=1)
Bit
Name
Function
Comment
19
18
17
0
0
PHA
Register address bit
Register address bit
Polarity A
Sign of current flow through coil A:
0: Current flows from OA1 pins to OA2 pins.
1: Current flows from OA2 pins to OA1 pins.
Magnitude of current flow through coil A. The range is
0 to 248, if hysteresis or offset are used up to their full
extent. The resulting value after applying hysteresis or
offset must not exceed 255.
16
15
14
13
12
11
10
9
CA7
CA6
CA5
CA4
CA3
CA2
CA1
CA0
Current A MSB
Current A LSB
www.trinamic.com
TRINAMIC [ TRINAMIC MOTION CONTROL GMBH & CO. KG. ]
