TPS54560
SLVSBN0 –MARCH 2013
www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
Table 1. ORDERING INFORMATION(1)
TJ
PACKAGE
PART NUMBER(2)
–40°C to 150°C
8 Pin HSOIC
TPS54560DDA
(1) For the most current package and ordering information see the Package Option Addendum at the end of this document, or see the TI
website at www.ti.com.
(2) The DDA package is also available in tape and reel packaging. Add an R suffix to the device type (TPS54560DDAR).
DEVICE INFORMATION
PIN CONFIGURATION
HSOIC PACKAGE
(TOP VIEW)
BOOT
VIN
1
2
3
4
8
7
6
5
SW
GND
COMP
FB
Thermal
Pad
9
EN
RT/CLK
PIN FUNCTIONS
PIN
NAME
I/O
DESCRIPTION
NO.
A bootstrap capacitor is required between BOOT and SW. If the voltage on this capacitor is below the
minimum required to operate the high side MOSFET, the output is switched off until the capacitor is
refreshed.
BOOT
1
O
VIN
EN
2
3
I
I
Input supply voltage with 4.5 V to 60 V operating range.
Enable pin, with internal pull-up current source. Pull below 1.2 V to disable. Float to enable. Adjust the input
undervoltage lockout with two resistors. See the Enable and Adjusting Undervoltage Lockout section.
Resistor Timing and External Clock. An internal amplifier holds this pin at a fixed voltage when using an
external resistor to ground to set the switching frequency. If the pin is pulled above the PLL upper threshold,
a mode change occurs and the pin becomes a synchronization input. The internal amplifier is disabled and
the pin is a high impedance clock input to the internal PLL. If clocking edges stop, the internal amplifier is re-
enabled and the operating mode returns to resistor frequency programming.
RT/CLK
4
I
FB
5
6
I
Inverting input of the transconductance (gm) error amplifier.
Error amplifier output and input to the output switch current (PWM) comparator. Connect frequency
compensation components to this pin.
COMP
O
GND
SW
7
8
9
–
I
Ground
The source of the internal high-side power MOSFET and switching node of the converter.
GND pin must be electrically connected to the exposed pad on the printed circuit board for proper operation.
Thermal Pad
–
2
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