WT6014
Digital Monitor Controller
Ver. 1.21 Jul-31-1998
DDC Interface
The DDC interface is a slave mode I
2
C interface with DDC1 function. It is fully compatible with
VEAS DDC1/2B standard. The functional block diagram is shown in the below.
Internal Data
ENACK
Data Buffer
SDA
I/O
VSYNC
MUX
Shift Register
R/W
Address Compare
MSB
ADDR
START
STOP
DDC2B
SCL
1 0 1 0 0 0 0
Address Register
START/STOP Detect
Handshake Control
After power on or reset the DDC interface, it is in DDC1 state. The shift register shifts out data to
SDA pin on the rising edge of VSYNC clock. Data format is an 8-bit byte followed by a null bit. Most
significant bit (MSB) is transmitted first. Every time when the ninth bit has been transmitted, the shift
register will load a data byte from data buffer (REG#18H). After loading data to the shift register, the
data buffer becomes empty and generates an INT0 interrupt. So the program must write one data byte
into REG#18 every nine VSYNC clocks.
Since the default values of data buffer(REG#22) and shift register are FFH, the SDA pin outputs
high level if no data had been written into data buffer after power on reset. When program finished
initialization and set the IEN_D bit to "1", the INT0 will occur because the data buffer is empty. The
INT0 service routine should check the DDC2B bit is "0" and then writes the first EDID data byte into
data buffer. When the second INT0 occurs, the INT0 service routine writes the second EDID data byte
into data buffer and so on.
SDA
VSYNC
Load data to
shift register
INT0
IEN_D
Bit7
1
2
3
9
10
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
18
Bit7
19
Weltrend Semiconductor, Inc.
9
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