W9864G6IH
5. PIN DESCRIPTION
PIN NUMBER
PIN NAME
FUNCTION
DESCRIPTION
Multiplexed pins for row and column address.
23 ~ 26, 22,
29 ~35
Row address: A0−A11. Column address: A0−A7.
A0−A11
Address
A10 is sampled during a precharge command to
determine if all banks are to be precharged or bank
selected by BS0, BS1.
Select bank to activate during row address latch time,
or bank to read/write during address latch time.
Multiplexed pins for data output and input.
Disable or enable the command decoder. When
command decoder is disabled, new command is
ignored and previous operation continues.
Command input. When sampled at the rising edge of
the clock
RAS
,
CAS
and
WE
define the
operation to be executed.
Referred to
RAS
Referred to
RAS
The output buffer is placed at Hi-Z (with latency of 2)
when DQM is sampled high in read cycle. In write
cycle, sampling DQM high will block the write
operation with zero latency.
System clock used to sample inputs on the rising
edge of clock.
CKE controls the clock activation and deactivation.
When CKE is low, Power Down mode, Suspend
mode, or Self Refresh mode is entered.
Power for input buffers and logic circuit inside DRAM.
Ground for input buffers and logic circuit inside
DRAM.
for I/O
Separated power from V
DD
, to improve DQ noise
immunity.
Separated ground from V
SS
, to improve DQ noise
immunity.
No connection.(The NC pin must connect to
20, 21
BS0, BS1
Bank Select
2, 4, 5, 7, 8, 10,
Data
11, 13, 42, 44,
DQ0−DQ15
45, 47, 48, 50,
Input/ Output
51, 53
19
CS
Chip Select
18
RAS
Row Address
Strobe
Column
Address Strobe
Write Enable
Input/output
mask
17
16
CAS
WE
UDQM
LDQM
CLK
39, 15
38
Clock Inputs
37
1, 14, 27
28, 41, 54
3, 9, 43, 49
6, 12, 46, 52
36, 40
CKE
V
DD
V
SS
V
DDQ
V
SSQ
NC
Clock Enable
Power
Ground
Power
buffer
Ground for I/O
buffer
No Connection
ground or floating.)
-5-
Publication Release Date:Mar. 31, 2008
Revision A05
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